CY7C373I-100JC Cypress Semiconductor Corp, CY7C373I-100JC Datasheet - Page 6

• Manufacturer Part Number: CY7C373I-100JC
• Description: IC CPLD 64 MACROCELL 84-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultralogic™r

Specifications of CY7C373I-100JC

• Memory Type: FLASH
• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 12.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of I /o: 64
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 3.3V/5V
• Family Name: FLASH370i
• # Macrocells: 64
• Number Of Usable Gates: 1600
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1269

Switching Characteristics
Document #: 38-03030 Rev. **
Combinatorial Mode Parameters
t
t
t
t
t
Input Registered/Latched Mode Parameters
t
t
t
t
t
t
Output Registered/Latched Mode Parameters
t
t
t
t
t
t
t
f
f
f
t
37x
Notes:
Parameter
12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met
11. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
MAX1
MAX2
MAX3
OH
–t
for the devices operating at the same ambient temperature and at the same power supply voltage.
IH
Input to Combinatorial Output
Input to Output Through Transparent Input or
Output Latch
Input to Output Through Transparent Input and
Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to
Combinatorial Output
Input Register Clock or Latch Enable to
Output Through Transparent Output Latch
Clock or Latch Enable to Output
Set-Up Time from Input to Clock or Latch
Enable
Register or Latch Data Hold Time
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch
Enable
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
Maximum Frequency with Internal Feedback
(Least of 1/t
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
t
Maximum Frequency of (2) CY7C373is with
External Feedback (Lesser of 1/(t
1/(t
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x
WH
WL
), 1/(t
+ t
S
WH
+ t
)
[7]
H
SCS
[1]
), or 1/t
[1]
, 1/(t
Description
CO
S
+ t
[1]
Over the Operating Range
)
[7]
[1]
H
[1]
), or 1/t
[1]
CO
[1]
CO
)
[7]
[7, 12]
+ t
S
[7]
[7]
) and
WL
[1]
+
[ 11 ]
153.8
7C373i–125
Min.
83.3
125
5.5
10
3
3
2
2
0
8
0
0
Max.
6.5
10
13
15
14
14
14
16
14
153.8
7C373i–100
Min.
100
10
12
80
3
3
2
2
6
0
0
0
Max.
6.5
12
15
16
16
16
16
18
16
7C373iL-83
Min.
62.5
125
7C373i–83
12
15
83
4
4
3
3
8
0
0
0
Max.
15
18
19
19
19
19
21
19
8
7C373iL–66
Min.
100
7C373i–66
10
15
20
66
50
5
5
4
4
0
0
0
CY7C373i
Max.
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20
22
24
24
24
24
26
10
24
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns