CY7C375I-125AC Cypress Semiconductor Corp, CY7C375I-125AC Datasheet - Page 5
![IC CPLD 128 MACROCELL 160LQFP](/photos/6/70/67052/428-160-tqfp_sml.jpg)
CY7C375I-125AC
Manufacturer Part Number
CY7C375I-125AC
Description
IC CPLD 128 MACROCELL 160LQFP
Manufacturer
Cypress Semiconductor Corp
Series
Ultralogic™r
Specifications of CY7C375I-125AC
Memory Type
CMOS
Programmable Type
In-System Reprogrammable™ (ISR™) CMOS
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of I /o
128
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-LQFP
Voltage
5V
Family Name
FLASH370i
# Macrocells
128
Number Of Usable Gates
3200
Frequency (max)
158.3MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
8
# I/os (max)
128
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1472
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C375I-125AC
Manufacturer:
CYPRESS
Quantity:
150
Company:
Part Number:
CY7C375I-125AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
dled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with F
PCI Compliance
The F
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The F
3.3V and 5.0V systems. All devices have two sets of V
one set, V
another set, V
always be connected to a 5.0V power supply. However, the
V
supply, depending on the output requirements. When V
pins are connected to a 5.0V source, the I/O voltage levels are
Operating Range
Document #: 38-03029 Rev. **
Commercial
Industrial
Military
Note:
LASH
CCIO
2.
LASH
T
Range
LASH
370i ensures compliance with the PCI AC specifications
LASH
A
pins may be connected to either a 3.3V or 5.0V power
is the “instant on” case temperature.
[2]
370i PLDs. Note that product term allocation is han-
370i family of CMOS CPLDs are fully compliant with
CCINT
370i family can be configured to operate in both
CCIO
, for internal operation and input buffers, and
, for I/O output drivers. V
–55°C to +125°C
Temperature
0 C to +70 C
40 C to +85 C
Ambient
CCINT
LASH
5V
5V
5V
V
V
CCINT
pins must
370i.”
LASH
CC
0.25V
0.5V
0.5V
CC
pins:
CCIO
370i
3.3V
3.3V
5V
compatible with 5.0V systems. When V
ed to a 3.3V source, the input voltage levels are compatible
with both 5.0V and 3.3V systems, while the output voltage lev-
els are compatible with 3.3V systems. There will be an addi-
tional timing delay on all output buffers when operating in 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
Design Tools
Development software for the CY7C375i is available from Cy-
press’s Warp™, Warp Professional™, and Warp Enterprise™
software packages. Please refer to the data sheets on these
products for more details. Cypress also actively supports al-
most all third-party design tools. Please refer to third-party tool
support for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65 C to +150 C
Ambient Temperature with
Power Applied ............................................ –55 C to +125 C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage .................................................... 12.5V
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
5V
V
OR
OR
CCIO
0.25V
0.5V
0.3V
0.3V
LASH
CC
370i I/Os and dedicated input pins.
or GND.
CCIO
pins are connect-
CY7C375i
Page 5 of 17