ATV2500BQL-25DC Atmel, ATV2500BQL-25DC Datasheet - Page 10

• Manufacturer Part Number: ATV2500BQL-25DC
• Description: IC CPLD QTR PWR L FEAT 40CERDIP
• Manufacturer: Atmel
• Series: ATV2500B(L) and BQ(L)r

Specifications of ATV2500BQL-25DC

• Programmable Type: UV Erasable
• Delay Time Tpd(1) Max: 25.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 24
• Number Of I /o: 24
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-CDIP (0.600", 15.24mm)
• Voltage: 5V
• Memory Type: OTP EPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: ATV2500BQL25DC

AC Characteristics
Input Test Waveforms and
Measurement Levels
Preload and Observability of Registered Outputs
The ATV2500Bs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V
appropriate register high; a V
of the polarity or other configuration bit settings.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
PD1
PD2
PD3
PD4
EA1
ER1
EA2
ER2
AW
AP
APF
Parameter
Input to Non-registered Output
Feedback to Non-registered
Output
Input to Non-registered Feedback
Feedback to Non-registered
Feedback
Input to Output Enable
Input to Output Disable
Feedback to Output Enable
Feedback to Output Disable
Asynchronous Reset Width
Asynchronous Reset to
Registered Output
Asynchronous Reset to
Registered Feedback
ATV2500B(Q)(L)
IH
level on the odd I/O pins will force the
IL
will force it low, independent
Min
6
-12
Max
12
12
12
12
12
12
15
12
8
8
Min
8
Output Test Load
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.
-15
Max
15
15
11
11
15
15
15
15
18
15
Min
12
-20
Max
20
20
15
15
20
20
20
20
22
19
Min
15
-25
Max
25
25
18
18
25
25
25
25
28
25
Min
18
-30
Max
30
30
20
20
30
30
30
30
30
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns