ATV2500BQ-20DC Atmel, ATV2500BQ-20DC Datasheet - Page 11

IC CPLD QTR POWER 200NS 40DIP

ATV2500BQ-20DC

Manufacturer Part Number
ATV2500BQ-20DC
Description
IC CPLD QTR POWER 200NS 40DIP
Manufacturer
Atmel
Series
ATV2500B(L) and BQ(L)r
Datasheet

Specifications of ATV2500BQ-20DC

Programmable Type
UV Erasable
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
24
Number Of I /o
24
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
40-DIP (0.600", 15.24mm)
Voltage
5V
Memory Type
OTP EPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATV2500BQ20DC
Power-up Reset
The registers in the ATV2500Bs are designed to reset dur-
ing power-up. At a point delayed slightly from V
V
state will depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the
uncertainty of how V
lowing conditions are required:
1. The V
2. After reset occurs, all input and feedback setup
3. The clock pin, and any signals from which clock
Parameter
t
V
RST
PRELOAD Cycle
Level Forced on
PR
RST
Odd I/O Pin
times must be met before driving the clock pin or
terms high, and
terms are derived, must remain stable during t
, all registers will be reset to the low state. The output
V
V
V
V
during
IH
IH
IH
IH
/V
/V
/V
/V
CC
IL
IL
IL
IL
rise must be monotonic,
CC
Q Select Pin
actually rises in the system, the fol-
State
High
High
Low
Low
Description
Power-up Reset Time
Power-up Reset Voltage
Even/Odd Select
High
High
Low
Low
CC
PR
crossing
.
Even Q1 State
after Cycle
High/Low
X
X
X
.
Even Q2 State
after Cycle
High/Low
X
X
X
Typ
600
3.8
Odd Q1 State
after Cycle
High/Low
X
X
X
1000
Max
4.5
Odd Q2 State
after Cycle
High/Low
Units
X
X
X
ns
V
11

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