ATF1508ASVL-20JC84 Atmel, ATF1508ASVL-20JC84 Datasheet - Page 7
![IC CPLD 20NS 84PLCC](/photos/6/70/67047/453-84-plcc_sml.jpg)
ATF1508ASVL-20JC84
Manufacturer Part Number
ATF1508ASVL-20JC84
Description
IC CPLD 20NS 84PLCC
Manufacturer
Atmel
Series
ATF1508ASV(L)r
Datasheet
1.ATF1508ASVL-20JU84.pdf
(28 pages)
Specifications of ATF1508ASVL-20JC84
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
128
Number Of I /o
64
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1508ASVL20JC84
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Programmable Pin-
keeper Option for
Inputs and I/Os
Speed/Power
Management
1408H–PLD–7/05
The ATF1508ASV(L) offers the option of programming all input and I/O pins so that “pin-
keeper” circuits can be utilized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Input Diagram
The ATF1508ASV(L) has several built-in speed and power management features. The
ATF1508ASV(L) contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power-savings for most
applications running at system speeds below 5 MHz.
To further reduce power, each ATF1508ASV(L) macrocell has a reduced-power bit fea-
ture. This feature allows individual macrocells to be configured for maximum power-
savings. This feature may be selected as a design option.
I/O Diagram
ATF1508ASV(L)
7