ATF1504ASVL-20JC84 Atmel, ATF1504ASVL-20JC84 Datasheet - Page 4
![IC CPLD 64MACROCELL LV LP 84PLCC](/photos/6/70/67047/453-84-plcc_sml.jpg)
ATF1504ASVL-20JC84
Manufacturer Part Number
ATF1504ASVL-20JC84
Description
IC CPLD 64MACROCELL LV LP 84PLCC
Manufacturer
Atmel
Series
ATF1504ASV(L)r
Datasheet
1.ATF1504ASV-15JU44.pdf
(31 pages)
Specifications of ATF1504ASVL-20JC84
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
64
Number Of I /o
64
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1504ASVL20JC84
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Description
The ATF1504ASV(L) is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matri-
ces increase usable gate count and the odds of successful pin-locked design
modifications.
The ATF1504ASV(L) has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic func-
tions. The ATF1504ASV(L) contains four such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
The ATF1504ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
ATF1504ASV(L)
4
1409J–PLD–6/05