ATF1504AS-10AC44 Atmel, ATF1504AS-10AC44 Datasheet - Page 9

• Manufacturer Part Number: ATF1504AS-10AC44
• Description: IC CPLD 64 MACROCELL 10NS 44TQFP
• Manufacturer: Atmel
• Series: ATF1504AS(L)r

Specifications of ATF1504AS-10AC44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 64
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Voltage: 5V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

Design Software
Support
Power-up Reset
Security Fuse Usage
0950N–PLD–07/02
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the
AC parameters, which include the data paths t
The ATF1504AS macrocell also has an option whereby the power can be reduced on a
per macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned-down, thereby reducing the overall power consumption
of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
ATF1504AS designs are supported by several industry-standard third-party tools. Auto-
mated fitters allow logic synthesis using a variety of high level description languages
and formats.
The ATF1504AS is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from V
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how V
system, the following conditions are required:
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving
3. The clock must remain stable during T
The ATF1504AS has two options for the hysteresis about the reset level, V
and Large. During the fitting process users may configure the device with the Power-up
Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large
option by including the flag “-power_reset” on the command line after “filename.POF”.
To allow the registers to be properly reinitialized with the Large hysteresis option
selected, the following condition is added:
4. If V
When the Large hysteresis option is active, I
amps as well.
A single fuse is provided to prevent unauthorized copying of the ATF1504AS fuse pat-
terns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
the clock pin high, and,
again.
CC
CC
falls below 2.0V, it must shut off completely before the device is turned on
rise must be monotonic,
D
.
CC
LAD
CC
is reduced by several hundred micro-
, t
crossing V
LAC
, t
IC
, t
ACL
ATF1504AS(L)
RST
, t
, all registers will be ini-
ACH
CC
actually rises in the
and t
SEXP
RST
.
, Small
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