ATF1502ASV-15JC44 Atmel, ATF1502ASV-15JC44 Datasheet - Page 3

• Manufacturer Part Number: ATF1502ASV-15JC44
• Description: IC CPLD 32 MACROCELL LV 44PLCC
• Manufacturer: Atmel
• Series: ATF1502ASVr

Specifications of ATF1502ASV-15JC44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

Figure 1-3.
1615J–PLD–01/06
32
Block Diagram
Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input
and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40
individual signals from the global bus. Each macrocell also generates a foldback logic term that
goes to a regional bus. Cascade logic between macrocells in the ATF1502ASV allows fast, effi-
cient generation of complex logic functions. The ATF1502ASV contains four such logic chains,
each capable of creating sum term logic with a fan-in of up to 40 product terms.
The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
Unused product terms are automatically disabled by the compiler to decrease power consump-
tion. A security fuse, when programmed, protects the contents of the ATF1502ASV. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project name,
part number, revision or date. The User Signature is accessible regardless of the state of the
security fuse.
The ATF1502ASV device is an in-system programmable (ISP) device. It uses the industry stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan
Description Language (BSDL). ISP allows the device to be programmed without removing it from
B
ATF1502ASV
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