ATF1502AS-10AC44 Atmel, ATF1502AS-10AC44 Datasheet - Page 6

• Manufacturer Part Number: ATF1502AS-10AC44
• Description: IC CPLD 32 MACROCELL 10NS 44TQFP
• Manufacturer: Atmel
• Series: ATF1502AS(L)r

Specifications of ATF1502AS-10AC44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Voltage: 4.75 V ~ 5.25 V
• Memory Type: EEPROM
• Circuit Type: Electrically Erasable
• Logic Function: Programmable
• Logic Type: CPLD
• Package Type: TQFP-44
• Special Features: Security Fuse
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Supply: 5.25 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device
• Other names: ATF1502AS-10AC

Input Diagram
I/O Diagram
Speed/Power
Management
6
ATF1502AS(L)
The ATF1502AS has several built-in speed and power management features. The
ATF1502AS contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power savings for most applications
running at system speeds below 50 MHz. This feature may be selected as a design option.
To further reduce power, each ATF1502AS macrocell has a reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
The ATF1502AS also has an optional power-down mode. In this mode, current drops to below
10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be
used to power down the part. The power-down option is selected in the design source file.
When enabled, the device goes into power-down when either PD1 or PD2 is high. In the
power-down mode, all internal logic signals are latched and held, as are any enabled outputs.
0995K–PLD–6/05