XC95216-20PQ160C Xilinx Inc, XC95216-20PQ160C Datasheet - Page 5
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XC95216-20PQ160C
Manufacturer Part Number
XC95216-20PQ160C
Description
IC CPLD 216 MCELL C-TEMP 160PQFP
Manufacturer
Xilinx Inc
Series
XC9500r
Specifications of XC95216-20PQ160C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
12
Number Of Macrocells
216
Number Of Gates
4800
Number Of I /o
133
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Voltage
5V
Memory Type
FLASH
Package
160PQFP
Family Name
XC9500
Device System Gates
4800
Number Of Macro Cells
216
Maximum Propagation Delay Time
20 ns
Number Of User I/os
133
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
50 MHz
Number Of Product Terms Per Macro
90
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC95216-20PQ160C
Manufacturer:
XILINX
Quantity:
656
Macrocell
Each XC9500 macrocell may be individually configured for
a combinatorial or registered function. The macrocell and
associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable. The product
DS063 (v5.5) June 25, 2007
Product Specification
36
R
Figure
Figure 3: XC9500 Macrocell Within Function Block
Allocator
Product
Term
3.
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
www.xilinx.com
Set/Reset
Global
term allocator associated with each macrocell selects how
the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Clocks
3
Global
XC9500 In-System Programmable CPLD Family
D/T
R
S
Q
OUT
PTOE
To
Fast CONNECTII
Switch Matrix
DS063_03_110501
To
I/O Blocks
5