XC2C256-7VQG100I Xilinx Inc, XC2C256-7VQG100I Datasheet - Page 2

• Manufacturer Part Number: XC2C256-7VQG100I
• Description: IC CR-II CPLD 256MCELL 100-VQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C256-7VQG100I

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 6000
• Number Of I /o: 80
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• For Use With: 122-1512 - KIT DESIGN CPLD W/BATT HOLDER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

XC2C256 CoolRunner-II CPLD
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 256
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 256 macrocell CPLD is I/O compatible
with various I/O standards (see
1.5V I/O compatible with the use of Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high-performance and
low power operation.
Supported I/O Standards
The CoolRunner-II 256 macrocell features LVCMOS,
LVTTL, SSTL and HSTL I/O implementations. See
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, resettable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
0.021
0
Table
100
75
50
25
11.68
0
1). This device is also
30
0
19.40
A
Figure 1: I
50
50
= 25°C)
Table 1
www.xilinx.com
27.01
70
(1)
100
CC
vs Frequency
Frequency (MHz)
38.18
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL I/O standards make use of a V
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V
I/O compatible with the use of Schmitt-trigger inputs
Table 1: I/O Standards for XC2C256
(1)For information on Vref, see XAPP399.
(2) LVCMOS15 requires Schmitt-trigger inputs.
100
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
IOSTANDARD
Frequency (MHz)
Attribute
150
45.54
120
(2)
200
56.32
150
Output
V
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
250
63.37
170
V
Input
CCIO
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
DS094 (v3.2) March 8, 2007
70.40
190
Input
V
0.75
1.25
N/A
N/A
N/A
N/A
N/A
Product Specification
(1)
1.5
REF
80.90
220
Termination
Voltage V
Board
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
REF
88.03
240
TT
pin
R