XC9572-15PC44C Xilinx Inc, XC9572-15PC44C Datasheet - Page 3

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XC9572-15PC44C

Manufacturer Part Number
XC9572-15PC44C
Description
IC CPLD 72 MACROCELL 44-PLCC
Manufacturer
Xilinx Inc
Series
XC9500r

Specifications of XC9572-15PC44C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
FLASH
Circuit Type
Advanced, FastFLASH™
Current, Supply
65 mA
Function Type
16-Bits
Logic Function
Programmable
Logic Type
CMOS
Number Of Pins
44
Package Type
PLCC-44
Power Requirements
-0.5 to 7 V
Setup Time
8 ns (Min.)
Special Features
Parallel, Tri-State
Temperature, Operating, Range
-40 to +85 °C
Voltage, Supply
5.5 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
122-1171

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associated output enable signals drive directly to the IOBs.
See
Function Block
Each Function Block, as shown in
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the Fast CONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Thirty-six inputs provide 72 true and com-
plement signals into the programmable AND-array to form
DS063 (v5.5) June 25, 2007
Product Specification
Figure
JTAG Port
1.
I/O/GCK
I/O/GSR
I/O/GTS
R
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
2 or 4
3
1
Figure
3
2, is comprised of
Controller
Figure 1: XC9500 Architecture
Blocks
JTAG
I/O
www.xilinx.com
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
Each FB (except for the XC9536) supports local feedback
paths that allow any number of FB outputs to drive into its
own programmable AND-array without going outside the
FB. These paths are used for creating very fast counters
and state machines where all state registers are within the
same FB.
XC9500 In-System Programmable CPLD Family
In-System Programming Controller
18
18
18
18
36
36
36
36
Macrocells
Macrocells
Macrocells
Macrocells
Function
Function
Function
Function
DS063_01_110501
Block N
Block 1
Block 2
Block 3
1 to 18
1 to 18
1 to 18
1 to 18
3

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