XC2C64A-7VQG100I Xilinx Inc, XC2C64A-7VQG100I Datasheet - Page 7

IC CR-II CPLD 64MCELL 100-VQFP

XC2C64A-7VQG100I

Manufacturer Part Number
XC2C64A-7VQG100I
Description
IC CR-II CPLD 64MCELL 100-VQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheets

Specifications of XC2C64A-7VQG100I

Features
Programmable
Package / Case
100-TQFP, 100-VQFP
Mounting Type
Surface Mount
Voltage
1.8V
Operating Temperature
-40°C ~ 85°C
Number Of I /o
64
Memory Type
CMOS
Programmable Type
In System Programmable
Number Of Macrocells
64
Delay Time Tpd(1) Max
6.7ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
4
Number Of Gates
1500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2C64A-7VQG100I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2C64A-7VQG100I
Manufacturer:
XILINX
0
Part Number:
XC2C64A-7VQG100I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
XC2C64A-7VQG100I
Quantity:
860
Internal Timing Parameters
DS311 (v2.3) November 19, 2008
Product Specification
Buffer Delays
T
T
T
T
T
T
T
P-term Delays
T
T
T
Macrocell Delay
T
T
T
T
T
T
T
T
Feedback Delays
T
T
I/O Standard Time Adder Delays 1.5V CMOS
T
T
T
I/O Standard Time Adder Delays 1.8V CMOS
T
T
T
AOI
OUT
OEM
OUT15
OUT18
IN
DIN
GCK
GSR
GTS
EN
CT
LOGI1
LOGI2
PDI
SUI
HI
ECSU
ECHO
COI
CDBL
F
HYS15
SLEW15
HYS18
SLEW
Symbol
R
Input buffer delay
Direct data register input delay
Global clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
Control term delay
Single P-term delay adder
Multiple P-term delay adder
Input to output valid
Setup before clock
Hold after clock
Enable clock setup time
Enable clock hold time
Clock to output valid
Set/reset to output valid
Clock doubler delay
Feedback delay
Macrocell to global OE delay
Hysteresis input adder
Output adder
Output slew rate adder
Hysteresis input adder
Output adder
Output slew rate adder
Parameter
(1)
www.xilinx.com
Min.
1.4
0.0
0.9
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Max.
1.7
2.6
1.6
2.4
2.7
1.9
5.3
2.0
0.5
0.4
0.5
0.4
1.7
1.5
1.7
4.0
0.9
4.0
3.0
3.5
0
0
-
-
-
-
XC2C64A CoolRunner-II CPLD
Min.
1.8
0.0
1.3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
2.4
4.0
2.5
3.5
3.9
2.8
6.1
2.5
0.8
0.8
0.7
0.7
2.0
3.0
1.7
6.0
1.5
6.0
4.0
5.0
0
0
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7

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