XA9572XL-15VQG44Q Xilinx Inc, XA9572XL-15VQG44Q Datasheet - Page 8

• Manufacturer Part Number: XA9572XL-15VQG44Q
• Description: IC CPLD 3.3V 72MCELL 44-VQFP
• Manufacturer: Xilinx Inc
• Series: XA9500XL XAr

Specifications of XA9572XL-15VQG44Q

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 72
• Number Of Gates: 1600
• Number Of I /o: 34
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Features: Automotive
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

XA9572XL Automotive CPLD
Device Part Marking and Ordering Combination Information
XA9500XL Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applica-
tions:
1. All automotive customers are required to keep the
2. Use a monotonic, fast ramp power supply to power up
8
Notes:
I-Grade: T
XA9572XL-15VQG44I
XA9572XL-15VQG64I
XA9572XL-15TQG100I
XA9572XL-15VQG44Q
XA9572XL-15VQG64Q
XA9572XL-15TQG100Q
Part Marking Number
Device Ordering and
Macrocell Power selection set to low, and the Logic
Optimization set to density when designing with ISE
software. These are the default settings when
XA9500XL devices are selected for design. These
settings are found on the Process Properties page for
Implement Design. See the ISE Online Help for details
on these properties.
XA9500XL . A V
required.
A
= –40° to +85°C; Q-Grade: T
CC
·
Operating Range
ramp time of less than 1 ms is
Device Type
(pin-to-pin
15.5 ns
15.5 ns
15.5 ns
15.5 ns
15.5 ns
15.5 ns
Speed
delay)
Package
Speed
Device
Speed Grade
Package Type
Pb -Free
Number of Pins
Temperature Range
A
= –40° to +105°C.
TQG100 100-pin
TQG100 100-pin
Symbol
VQG44
VQG64
VQG44
VQG64
Example: XA9572XL
Pkg.
Sample package with part marking.
1
XA9572XL
TQG100
15I
www.xilinx.com
No. of
44-pin
64-pin
44-pin
64-pin
Pins
3. Do not float I/O pins during device operation. Floating
4. Do not drive I/O pins without V
5. Sink current when driving LEDs. Because all Xilinx
6. Avoid external pull-down resistors. Always use external
-15
I/O pins can increase I
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
I/O pins should be appropriately terminated with
keeper/bus-hold. Unused I/Os can also be configured
as C
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to V
will give the brightest solution.
pull-up resistors if external termination is required. This
is because the XC9500XL Automotive CPLD, which
R
TQ
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
GND
Quad Flat Pack (VQFP)
Quad Flat Pack (VQFP)
Quad Flat Pack (VQFP)
Quad Flat Pack (VQFP)
(programmable GND).
G
Package Type
100
This line not
related to device
part number
I
CC
as input buffers will draw
CC
DS599 (v1.1) April 3, 2007
CC
/V
Product Specification
. Consequently, this
CCIO
powered.
Operating
Range
Q
Q
Q
I
I
I
(1)
R