EPM7256AETC100-5N Altera, EPM7256AETC100-5N Datasheet

IC MAX 7000 CPLD 256 100-TQFP

EPM7256AETC100-5N

Manufacturer Part Number
EPM7256AETC100-5N
Description
IC MAX 7000 CPLD 256 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet

Specifications of EPM7256AETC100-5N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000A
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
250MHz
Propagation Delay Time
5.5ns
Number Of Logic Blocks/elements
16
# I/os (max)
84
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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Features...
Altera Corporation
DS-M7000A-4.5
September 2003, ver. 4.5
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
Data Sheet
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
or the
®
) architecture (see
®
MAX 7000B Programmable Logic Device Family Data
MAX 7000AE
Includes
MAX 7000 Programmable Logic Device Family
Table
1)
Programmable Logic
MAX 7000A
Data Sheet
Device
Sheet.
1

Related parts for EPM7256AETC100-5N

EPM7256AETC100-5N Summary of contents

Page 1

... September 2003, ver. 4.5 Features... f Altera Corporation DS-M7000A-4.5 Includes MAX 7000AE ® High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX ® ) architecture (see 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ...

Page 2

... Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins EPM7256AE 5,000 256 8 16 164 5.5 3.9 2.5 3.5 172.4 Altera Corporation EPM7512AE 10,000 512 32 212 7.5 5.6 3.0 4.7 116.3 ...

Page 3

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF and netlist files, library of parameterized modules (LPM), ...

Page 4

... All Ultra FineLine BGA packages are footprint-compatible via the SameFrame design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See details. (3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts ...

Page 5

... MAX 7000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software ...

Page 6

... I/O control blocks The MAX 7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices. Altera Corporation ...

Page 7

... INPUT/GCLRn Output Enables (1) I I/O Control Block I I/O Control Block Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables. EPM7512AE devices have 10 output enables. Altera Corporation MAX 7000A Programmable Logic Device Data Sheet LAB Macrocells LAB C PIA ...

Page 8

... Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. Figure 2 shows a MAX 7000A macrocell. ...

Page 9

... The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: Global clock signal ...

Page 10

... Figure 3. MAX 7000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders ) is incurred when SEXP Figure 3 shows how shareable expanders Product-Term Select Matrix Altera Corporation Macrocell Product-Term Logic Macrocell Product-Term Logic ...

Page 11

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB ...

Page 12

... LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Preset Clock Clear Preset Clock Clear To Next Macrocell Figure 5 shows how the PIA signals are routed Altera Corporation Macrocell Product- Term Logic Macrocell Product- Term Logic ...

Page 13

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 5. MAX 7000A PIA Routing PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable, and path-dependent, the MAX 7000A PIA has a predictable delay. The PIA makes a design’s timing performance easy to predict ...

Page 14

... The MAX 7000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic Global Output Enable Signals (1) OE Select Multiplexer VCC GND Open-Drain Output Slew-Rate Control Altera Corporation , the output is CC ...

Page 15

... EPM7128AE device in a 100-pin FineLine BGA package to an EPM7512AE device in a 256-pin FineLine BGA package. The Altera design software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure 7 ...

Page 16

... ISP simplifies the manufacturing flow by allowing devices to be mounted on a PCB with standard pick-and-place equipment before they are programmed. MAX 7000A devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera MasterBlaster serial/USB communications cable, ByteBlasterMV parallel port download cable, and BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e ...

Page 17

... EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. ...

Page 18

... The ISP times for a stand-alone verification of a single MAX 7000A device can be calculated from the following formula: Cycle VTCK -------------------------------- VER VPULSE f TCK where Verify time VER t = Sum of the fixed times to verify the EEPROM cells VPULSE Cycle = Number of TCK cycles to verify a device VTCK Altera Corporation ...

Page 19

... EPM7128AE 2.02 EPM7256AE 2.05 EPM7512AE 2.09 EPM7128A (1) 5.19 EPM7256A (1) 6.59 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet The programming times described in with the worst-case method using the enhanced ISP algorithm. & Cycle Values TCK Programming t (s) Cycle PPULSE 2.00 55,000 2 ...

Page 20

... For more information, see the The Altera software can use text- or waveform-format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation ...

Page 21

... These instructions are used when programming MAX 7000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam STAPL File, JBC File, or SVF File via an embedded processor or test equipment. Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Description ...

Page 22

... Notes: (1) The most significant bit (MSB the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST. Tables 9 Boundary-Scan Register Length 96 192 ...

Page 23

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 8 shows timing information for the JTAG signals. Figure 8. MAX 7000A JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 11 shows the JTAG timing parameters and values for MAX 7000A devices. Table 11. JTAG Timing Parameters & ...

Page 24

... MAX 7000A MultiVolt I/O support. Table 12. MAX 7000A MultiVolt I/O Support V Voltage Input Signal (V) CCIO 2.5 v 2 for the t LPA parameters. levels lower than 3.0 V CCIO instead of t OD2 Output Signal (V) 3.3 5.0 2 Altera Corporation option turned on LAD LAC IC . Inputs can OD1 3.3 5 ...

Page 25

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Open-Drain Output Option MAX 7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. This output can also provide an additional wired-OR plane ...

Page 26

... EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in erased during early stages of the production flow. power planes can be powered in any CCINT Figure 9. Test patterns can be used and then Altera Corporation and V CCINT CCIO ...

Page 27

... STG T Ambient temperature A T Junction temperature J Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 9. MAX 7000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions ...

Page 28

... Input fall time F 28 Conditions (3), (13) (3) (3) (4) Commercial range Industrial range (5) Commercial range Industrial range (5) Extended range (5) Min Max Unit 3.0 3.6 V 3.0 3.6 V 2.3 2.7 V 3.0 3.6 V –0.5 5. CCIO 0 70 ° C –40 85 ° ° C –40 105 ° C –40 130 ° Altera Corporation ...

Page 29

... Value of I/O pin pull-up resistor ISP during in-system programming or during power-up Table 16. MAX 7000A Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance I/O Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (6) Conditions I = – CCIO I = –0 ...

Page 30

... MAX 7000A Programmable Logic Device Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) For EPM7128A and EPM7256A devices only, V ...

Page 31

... MAX 7000A device timing can be analyzed with the Altera software, a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation ...

Page 32

... See Application Note 94 (Understanding MAX 7000 Timing) information. Output Register Parallel Delay Delay PEXP PRE t t CLR COMB t t FSU t FH Fast Input Delay Figure 12 shows the timing relationship Altera Corporation OD1 OD2 OD3 I/O Delay for more ...

Page 33

... F driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared Expander Parallel Expander (Logic Array Output) Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Combinatorial Mode t IN Input Pin t IO I/O Pin PIA Delay ...

Page 34

... Altera Corporation Unit -10 Max 6 9 9.7 ns MHz 9.7 ns MHz ...

Page 35

... Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -4 Min Max 0.7 0.7 2.3 1.9 0.5 1.5 0 ...

Page 36

... PIA delay PIA t Low-power adder LPA 36 Conditions -4 Min Max 1.2 0.6 0.8 1.2 1.2 (2) 0.9 (6) 2.5 Note (1) Speed Grade -7 -10 Min Max Min Max 2.0 2.5 1.0 1.2 1.3 1.9 1.9 2.6 1.9 2.6 1.5 2.1 4.0 5.0 Altera Corporation Unit ...

Page 37

... Minimum global clock CNT period f Maximum internal CNT global clock frequency t Minimum array clock ACNT period f Maximum internal ACNT array clock frequency Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (1) Conditions -4 Min Max 4.5 ( 4.5 (2) (2) 2.8 (2) 0.0 2 ...

Page 38

... Altera Corporation Unit ...

Page 39

... Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -4 Min Max 0.6 1.0 1.3 1.3 (2) 1.0 (6) 3.5 Note (1) Speed Grade -7 ...

Page 40

... Altera Corporation Unit 6 9 MHz ns MHz ...

Page 41

... Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB t Array clock delay IC Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -5 Min Max 0.7 0.7 2.5 2.0 0.4 1.6 0 1.3 ...

Page 42

... Register clear time CLR t PIA delay PIA t Low-power adder LPA 42 Conditions -5 Min Max 0.7 1.1 1.4 1.4 (2) 1.4 (6) 4.0 Note (1) Speed Grade -7 -10 Min Max Min Max 1.0 1.3 1.6 2.0 2.0 2.7 2.0 2.7 2.0 2.6 4.0 5.0 Altera Corporation Unit ...

Page 43

... Minimum global clock CNT period f Maximum internal CNT global clock frequency t Minimum array clock ACNT period f Maximum internal ACNT array clock frequency Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (1) Conditions -5 Min Max 5.5 ( 5.5 (2) (2) 3.9 (2) 0.0 2 ...

Page 44

... Altera Corporation Unit ...

Page 45

... EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -5 Min Max 1.2 0.8 1.0 1.6 1.6 (2) 1.7 (6) 4.0 Note (1) Speed Grade ...

Page 46

... Altera Corporation Unit MHz ns MHz ...

Page 47

... Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -7 Min Max 0.7 0.7 3.1 2.7 0.4 2.2 1 ...

Page 48

... PIA delay PIA t Low-power adder LPA 48 Conditions -7 Min Max 1.8 1.0 1.7 1.0 1.0 (2) 3.0 (6) 4.5 Note (1) Speed Grade -10 -12 Min Max Min Max 2.3 2.9 1.3 1.7 2.2 2.7 1.4 1.7 1.4 1.7 4.0 4.8 5.0 5.0 Altera Corporation Unit ...

Page 49

... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (1) Conditions -6 Min Max Min 6.0 ( 6.0 (2) (2) 4.2 5.3 (2) 0 ...

Page 50

... Altera Corporation Unit Max 1.1 ns 1.1 ns 3.9 ns 5.1 ns 1.3 ns 4.9 ns 4.9 ns 0.0 ns 0.9 ns 1.4 ns 5 ...

Page 51

... Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -6 Min Max Min 1.7 1.7 2.4 2.4 1.0 3.1 3.1 (2) 0.9 (6) 11 ...

Page 52

... Altera Corporation Unit Max 12 12.8 ns MHz 12.8 ns MHz ...

Page 53

... Register setup time SU t Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -6 Min Max Min 0.3 0.3 2.4 2.8 0.5 2.5 2.5 0 ...

Page 54

... CCINT The P value, which depends on the device output load characteristics IO and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The I value depends on the switching frequency and the application CCINT logic. The I value is calculated with the following equation: ...

Page 55

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet The parameters in this equation are Number of macrocells with the Turbo Bit option turned TON on, as reported in the MAX+PLUS II Report File (.rpt Number of macrocells in the device DEV MC = Total number of macrocells in the design, as reported in ...

Page 56

... MAX 7000A devices. EPM7064AE 227.3 MHz High Speed Typical I Active (mA) 144.9 MHz Low Power 200 250 192.3 MHz High Speed 108.7 MHz Low Power 200 250 3 Room Temperature 60 High Speed 125.0 MHz 20 Low Power 100 Frequency (MHz) Altera Corporation 222.2 MHz 200 250 ...

Page 57

... MAX 7000A Programmable Logic Device Data Sheet EPM7512AE 172.4 MHz High Speed Typical I Active (mA) 102.0 MHz 100 200 See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Figures 14 through 23 show the package pin-out diagrams for MAX 7000A devices. 39 I/O 38 ...

Page 58

... I/O 20 I EPM7128A I/O 24 EPM7128AE I/O 25 VCCIO 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 GND 32 A1 Ball Pad Corner I/O 73 I/O 72 GND 71 I/O/TDO 70 I/O 69 I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O Altera Corporation ...

Page 59

... Figure 17. 100-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Figure 18. 100-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Ball A1 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Pin 1 EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE ...

Page 60

... Package outline not drawn to scale Figure 20. 169-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale Indicates location of Ball Indicates location of Pin 1 Pin 1 EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Pin 37 . EPM7064AE EPM7128A EPM7128AE EPM7256AE Pin 109 Pin Altera Corporation A1 Ball Pad Corner ...

Page 61

... Figure 21. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale Pin 1 Pin 53 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet . EPM7256A EPM7256AE EPM7512AE Pin 157 Pin 105 61 ...

Page 62

... MAX 7000A Programmable Logic Device Data Sheet Figure 22. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates Location of Ball A1 62 EPM7512AE Altera Corporation A1 Ball Pad Corner ...

Page 63

... EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Revision History Altera Corporation MAX 7000A Programmable Logic Device Data Sheet . The information contained in the MAX 7000A Programmable Logic Device Data Sheet version 4.5 supersedes information published in previous versions. Version 4.5 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4 ...

Page 64

... Altera's standard warranty, but reserves the right Applications Hotline: to make changes to any products and services at any time without notice. Altera assumes no (800) 800-EPLD responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. ...

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