EPM7128AETC144-5N Altera, EPM7128AETC144-5N Datasheet - Page 33

• Manufacturer Part Number: EPM7128AETC144-5N
• Description: IC MAX 7000 CPLD 128 144-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7128AETC144-5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 100
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Voltage: 2.5V, 3.3V
• Memory Type: CMOS
• Number Of Logic Elements/cells: 8
• Family Name: MAX 7000A
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 250MHz
• Propagation Delay Time: 5ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 100
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2585; EPM7128AETC144-5N

Altera Corporation
Figure 12. MAX 7000A Switching Waveforms
t
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 2 ns. Inputs are
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Clock Pin
Input Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
t
t
IN
t
t
SU
IN
IO
t
MAX 7000A Programmable Logic Device Data Sheet
t
ACH
CH
t
t
H
t
t
t
GLOB
PIA
IN
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
t
CLR
, t
PRE
t
OD
t
OD
t
PIA
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