EPM7192SQC160-10N Altera, EPM7192SQC160-10N Datasheet - Page 9
![IC MAX 7000 CPLD 192 160-PQFP](/photos/6/70/67068/544-160-pqfp_sml.jpg)
EPM7192SQC160-10N
Manufacturer Part Number
EPM7192SQC160-10N
Description
IC MAX 7000 CPLD 192 160-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7192SQC160-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
12
Number Of Macrocells
192
Number Of Gates
3750
Number Of I /o
124
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
12
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2054
EPM7192SQC160-10N
EPM7192SQC160-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7192SQC160-10N
Manufacturer:
ALTERA31
Quantity:
921
Part Number:
EPM7192SQC160-10N
Manufacturer:
ALTERA
Quantity:
20 000
Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Altera Corporation
36 Signals
from PIA
Logic Array
Product Ter
16 Expander
T T ms
Each LAB is fed by the following signals:
■
■
■
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in
Product-
Select
Matrix
Ter
T T m
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Shared Logic
Expanders
Parallel Logic
Expanders
(from other
macrocells)
MAX 7000 Programmable Logic Device Family Data Sheet
Global
Clear
Select
Clear
Global
Clocks
2
VCC
Enable
Clock/
Select
Fast Input
Select
D/T
ENA
Figure
CLRN
PRN
to PIA
Q
Programmable
Register
Register
3.
Bypass
From
I/O pin
To I/O
Control
Block
9