EPM7128SQC100-7 Altera, EPM7128SQC100-7 Datasheet - Page 44
![IC MAX 7000 CPLD 128 100-PQFP](/photos/6/70/67066/544-100-pqfp_sml.jpg)
EPM7128SQC100-7
Manufacturer Part Number
EPM7128SQC100-7
Description
IC MAX 7000 CPLD 128 100-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7128SQC100-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2040
EPM7128SQC100-7
EPM7128SQC100-7
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128SQC100-7
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EPM7128SQC100-7
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EPM7128SQC100-7
Manufacturer:
ALTERA
Quantity:
531
Part Number:
EPM7128SQC100-7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM7128SQC100-7F
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EPM7128SQC100-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
44
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 31. EPM7128S External Timing Parameters
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Output data hold time after
clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
Tables 31
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(2)
C1 = 35 pF
(4)
(4)
(5)
Conditions
and
32
(3)
show the EPM7128S AC operating conditions.
147.1
147.1
166.7
Min Max Min Max Min Max Min Max
3.4
2.5
0.0
1.8
3.0
3.0
1.0
0.0
3.0
3.0
0.9
3.0
Note (1)
-6
6.0
6.0
4.0
6.5
6.8
6.8
125.0
125.0
166.7
6.0
0.0
3.0
0.5
3.0
3.0
3.0
2.0
3.0
3.0
3.0
1.0
-7
Speed Grade
7.5
7.5
4.5
7.5
8.0
8.0
100.0
100.0
125.0
7.0
0.0
3.0
0.5
4.0
4.0
2.0
5.0
4.0
4.0
4.0
1.0
-10
10.0
10.0
10.0
10.0
10.0
5.0
Altera Corporation
100.0
11.0
76.9
76.9
0.0
3.0
0.0
5.0
5.0
4.0
4.0
6.0
6.0
6.0
1.0
-15
15.0
15.0
15.0
13.0
13.0
8.0
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns