EPM2210F324I5 Altera, EPM2210F324I5 Datasheet - Page 38
![IC MAX II CPLD 2210 LE 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EPM2210F324I5
Manufacturer Part Number
EPM2210F324I5
Description
IC MAX II CPLD 2210 LE 324-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM2210F324I5
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of I /o
272
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
2210
For Use With
P0305 - KIT MAX II MICRO
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2269
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
EPM2210F324I5
Manufacturer:
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Quantity:
101
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EPM2210F324I5
Manufacturer:
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Part Number:
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2–30
Slew-Rate Control
Open-Drain Output
Programmable Ground Pins
MAX II Device Handbook
Table 2–6. Programmable Drive Strength
The output buffer for each MAX II device I/O pin has a programmable output slew-
rate control that can be configured for low noise or high-speed performance. A faster
slew rate provides high-speed transitions for high-performance systems. However,
these fast transitions may introduce noise transients into the system. A slow slew rate
reduces system noise, but adds a nominal output delay to rising and falling edges.
The lower the voltage standard (for example, 1.8-V LVTTL) the larger the output
delay when slow slew is enabled. Each I/O pin has an individual slew-rate control,
allowing the designer to specify the slew rate on a pin-by-pin basis. The slew-rate
control affects both the rising and falling edges.
MAX II devices provide an optional open-drain (equivalent to open-collector) output
for each I/O pin. This open-drain output enables the device to provide system-level
control signals (for example, interrupt and write enable signals) that can be asserted
by any of several devices. This output can also provide an additional wired-OR plane.
Each unused I/O pin on MAX II devices can be used as an additional ground pin.
This programmable ground feature does not require the use of the associated LEs in
the device. In the Quartus II software, unused pins can be set as programmable GND
on a global default basis or they can be individually assigned. Unused pins also have
the option of being set as tri-stated input pins.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Note to
(1) The I
is specified by the I/O standard. The I
maximum, where the V
condition is V
I/O Standard
Table
OH
current strength numbers shown are for a condition of a V
2–6:
OUT
= 1.7 V and the I
OL
maximum is specified by the I/O standard. For 2.5-V LVTTL/LVCMOS, the I
OL
condition is V
OL
current strength numbers shown are for a condition of a V
(Note 1)
IOH/IOL Current Strength Setting (mA)
OUT
= 0.7 V.
OUT
16
14
= V
8
8
4
7
6
3
4
2
OH
minimum, where the V
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
OH
minimum
OUT
OH
I/O Structure
= V
OL