EPM3512AFC256-10 Altera, EPM3512AFC256-10 Datasheet - Page 38
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EPM3512AFC256-10
Manufacturer Part Number
EPM3512AFC256-10
Description
IC MAX 3000A CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AFC256-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
208
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 3000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
32
# I/os (max)
208
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2279
Available stocks
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Manufacturer
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Price
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MAX 3000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
38
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 25. EPM3512A Internal Timing Parameters (Part 2 of 2)
Symbol
These values are specified under the recommended operating conditions, as shown in
Figure 11 on page 27
These values are specified for a PIA fan–out of one LAB (16 macrocells). For each additional LAB fan–out in these
devices, add an additional 0.1 ns to the PIA timing value.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
These parameters are measured with a 16–bit loadable, enabled, up/down counter programmed into each LAB.
The t
running in low–power mode.
LPA
Output buffer and pad delay,
slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
parameter must be added to the t
CCIO
CCIO
CCIO
CCIO
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
for more information on switching waveforms.
LAD
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(2)
(5)
Conditions
, t
LAC
, t
IC
, t
EN
, t
SEXP
Min
2.1
0.6
1.6
1.4
, t
ACL
-7
Note (1)
, and t
Max
Speed Grade
6.0
4.0
4.5
9.0
4.0
1.3
0.6
1.8
1.0
1.7
1.0
1.0
3.0
4.5
CPPW
LAD
parameters for macrocells
Min
3.0
0.8
1.6
1.4
Table 13 on page
parameter into the signal
-10
Altera Corporation
Max
10.0
6.5
5.0
5.5
5.0
1.7
0.8
2.3
1.3
2.2
1.4
1.4
4.0
5.0
LPA
parameter
23. See
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns