EPM7256AEFC256-7 Altera, EPM7256AEFC256-7 Datasheet - Page 7

IC MAX 7000 CPLD 256 256-FBGA

EPM7256AEFC256-7

Manufacturer Part Number
EPM7256AEFC256-7
Description
IC MAX 7000 CPLD 256 256-FBGA
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet

Specifications of EPM7256AEFC256-7

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000A
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2347

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Altera Corporation
Figure 1. MAX 7000A Device Block Diagram
Note:
(1)
EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.
EPM7512AE devices have 10 output enables.
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
6 or 10 Output Enables (1)
Control
Control
Block
Block
I/O
I/O
Logic Array Blocks
The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
6
6
2 to 16
2 to 16
2 to 16
2 to 16
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
1. Multiple LABs are linked together via the PIA, a global bus that
LAB A
LAB C
Macrocells
Macrocells
33 to 48
1 to 16
2 to 16
2 to 16
16
16
36
36
MAX 7000A Programmable Logic Device Data Sheet
PIA
36
36
2 to 16
2 to 16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 or 10 Output Enables (1)
2 to 16
2 to 16
2 to 16
2 to 16
Control
Control
Block
Block
I/O
I/O
6
6
2 to 16 I/O
2 to 16 I/O
7

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