EPM7064SLC44-7N Altera, EPM7064SLC44-7N Datasheet - Page 35
![IC MAX 7000 CPLD 64 44-PLCC](/photos/6/70/67054/544-44-plcc_sml.jpg)
EPM7064SLC44-7N
Manufacturer Part Number
EPM7064SLC44-7N
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7064SLC44-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 7000S
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
166.7MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2014
EPM7064SLC44-7N
EPM7064SLC44-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064SLC44-7N
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EPM7064SLC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 23. MAX 7000 & MAX 7000E External Timing Parameters
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
Global clock setup time of fast input
Global clock hold time of fast input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear and
preset
Output data hold time after clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
(2)
(2)
(3)
(5)
(5)
(6)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
MAX 7000 Programmable Logic Device Family Data Sheet
(4)
MAX 7000E (-12P)
125.0
Min
90.9
90.9
7.0
0.0
3.0
0.0
4.0
4.0
3.0
4.0
5.0
5.0
5.0
1.0
Note (1)
Max
12.0
12.0
12.0
11.0
11.0
Speed Grade
6.0
MAX 7000E (-12)
MAX 7000 (-12)
125.0
Min
10.0
90.9
90.9
0.0
3.0
0.0
4.0
4.0
4.0
4.0
5.0
5.0
5.0
1.0
Max
12.0
12.0
12.0
11.0
11.0
6.0
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35