EPM240T100C5 Altera, EPM240T100C5 Datasheet - Page 67

• Manufacturer Part Number: EPM240T100C5
• Description: IC MAX II CPLD 240 LE 100-TQFP
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240T100C5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-1146

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Figure 5–2. MAX II Device Timing Model
Preliminary and Final Timing
© August 2009 Altera Corporation
I/O Pin
INPUT
I/O Input Delay
f
t
IN
The timing characteristics of any signal path can be derived from the timing model
and parameters of a particular device. External timing parameters, which represent
pin-to-pin timing delays, can be calculated as the sum of internal parameters.
Refer to the
Handbook for more information.
This section describes and specifies the performance, internal, external, and UFM
timing specifications. All specifications are representative of the worst-case supply
voltage and junction temperature conditions.
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 5–13. MAX II Device Timing Model Status
EPM240
EPM240Z
EPM570
EPM570Z
Input Routing
Global Input Delay
Memory
Delay
Flash
User
t
DL
t
GLOB
Device
(1)
(1)
Data-In/LUT Chain
Understanding Timing in MAX II Devices
Table 5–13
To Adjacent LE
Register Control
LUT Delay
t
Logic Element
Delay
LUT
t
C
t
R4
shows the status of the MAX II device timing models.
Preliminary
t
COMB
t
t
t
—
—
—
—
t
PRE
CLR
CO
SU
t
H
Register Delays
t
C4
(Part 1 of 2)
Data-Out
Combinational Path Delay
From Adjacent LE
Output Routing
chapter in the MAX II Device
Final
v
v
v
v
t
Delay
FASTIO
t
IODR
t
IOE
Output and Output Enable
Data Delay
Output
Delay
t
t
t
OD
XZ
MAX II Device Handbook
ZX
I/O Pin
5–9