EPM240F100C5N Altera, EPM240F100C5N Datasheet - Page 41
![IC MAX II CPLD 240 LE 100-FBGA](/photos/6/71/67105/544-100-fbga_sml.jpg)
EPM240F100C5N
Manufacturer Part Number
EPM240F100C5N
Description
IC MAX II CPLD 240 LE 100-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM240F100C5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.7ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
240
Number Of Macrocells
192
Number Of I /o
80
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
240
Family Name
MAX II
# Macrocells
192
Frequency (max)
1.8797GHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
24
# I/os (max)
80
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1709
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM240F100C5N
Manufacturer:
NSC
Quantity:
560
Company:
Part Number:
EPM240F100C5N
Manufacturer:
ALTERA
Quantity:
591
Part Number:
EPM240F100C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: MAX II Architecture
Document Revision History
Document Revision History
Table 2–8. Document Revision History
© October 2008 Altera Corporation
Date and Revision
October 2008,
version 2.2
March 2008,
version 2.1
December 2007,
version 2.0
December 2006,
version 1.7
August 2006,
version 1.6
July 2006,
vervion 1.5
February 2006,
version 1.4
August 2005,
version 1.3
December 2004,
version 1.2
June 2004,
version 1.1
Changes Made
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Table 2–8
Updated
Updated
Updated New Document Format.
Updated “Schmitt Trigger” section.
Updated “Clear and Preset Logic Control” section.
Updated “MultiVolt Core” section.
Updated “MultiVolt I/O Interface” section.
Updated Table 2–7.
Added “Referenced Documents” section.
Minor update in “Internal Oscillator” section. Added document
revision history.
Updated functional description and I/O structure sections.
Minor content and table updates.
Updated “LAB Control Signals” section.
Updated “Clear and Preset Logic Control” section.
Updated “Internal Oscillator” section.
Updated Table 2–5.
Removed Note 2 from Table 2-7.
Added a paragraph to page 2-15.
Added CFM acronym. Corrected Figure 2-19.
Table 2–4
“I/O Standards and Banks”
shows the revision history for this chapter.
and
Table
2–6.
section.
Summary of Changes
Updated document with
MAX IIZ information.
MAX II Device Handbook
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