EPM240M100C5N Altera, EPM240M100C5N Datasheet - Page 57

• Manufacturer Part Number: EPM240M100C5N
• Description: IC MAX II CPLD 240 LE 100-MBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240M100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 544-1706

Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
Figure 4–5. Power-Up Characteristics for MAX II, MAX IIG, and MAX IIZ Devices
Notes to
(1) Time scale is relative.
(2)
© October 2008 Altera Corporation
Figure 4–5
Figure
1.55 V
1.55 V
3.3 V
1.8 V
1.4 V
3.3 V
2.5 V
1.7 V
1.4 V
3.3 V
1.8 V
1.4 V
0 V
0 V
0 V
V
V
V
assumes all V
4–5:
CCINT
CCINT
CCINT
1
After SRAM configuration, all registers in the device are cleared and released into
user function before I/O tri-states are released. To release clears after tri-states are
released, use the DEV_CLRn pin option. To hold the tri-states beyond the power-up
configuration time, use the DEV_OE pin option.
CCIO
Tri-State
Tri-State
Tri-State
banks power up simultaneously with the V
t
t
t
CONFIG
CONFIG
CONFIG
MAX II Device
MAX IIG Device
MAX IIZ Device
Approximate Voltage
for SRAM Download Start
User Mode
User Mode
Operation
Operation
User Mode
Operation
minimum 10 µs
CCINT
profile shown. If not, t
V
Approximate Voltage
for SRAM Download Start
CCINT
Approximate Voltage
for SRAM Download Start
dips below this level
Tri-State
to 0 V if the V
must be powered down
Tri-State
Tri-State
CONFIG
(Note
CCINT
Device Resets
the SRAM and
Tri-States I/O Pins
stretches out until all V
Device Resets
the SRAM and
Tri-States I/O Pins
1),
(2)
t
User Mode
CONFIG
Operation
MAX II Device Handbook
CCIO
banks are powered.
4–7