ATF1504AS-10JC44 Atmel, ATF1504AS-10JC44 Datasheet - Page 8
![IC CPLD 64 MACROCELL 10NS 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATF1504AS-10JC44
Manufacturer Part Number
ATF1504AS-10JC44
Description
IC CPLD 64 MACROCELL 10NS 44PLCC
Manufacturer
Atmel
Series
ATF1504AS(L)r
Specifications of ATF1504AS-10JC44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
64
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Product Terms Per Macro
40
Maximum Operating Frequency
125 MHz
Delay Time
7.5 ns
Number Of Programmable I/os
32
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATF1504AS-10JC44
Manufacturer:
ATMEL
Quantity:
15
Part Number:
ATF1504AS-10JC44
Manufacturer:
ATEMEL
Quantity:
20 000
Programmable Pin-
keeper Option for
Inputs and I/Os
Input Diagram
Speed/Power
Management
I/O Diagram
8
ATF1504AS(L)
The ATF1504AS offers the option of programming all input and I/O pins so that pin-
keeper circuits can be utilized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
The ATF1504AS has several built-in speed and power management features. The
ATF1504AS contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
To further reduce power, each ATF1504AS macrocell has a Reduced Power bit feature.
This feature allows individual macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1504AS also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power-down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
0950O–PLD–7/05