EPM7256BFC256-7 Altera, EPM7256BFC256-7 Datasheet - Page 19

• Manufacturer Part Number: EPM7256BFC256-7
• Description: IC MAX 7000 CPLD 256 256-FBGA
• Manufacturer: Altera
• Series: MAX® 7000Br

Specifications of EPM7256BFC256-7

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 2.375 V ~ 2.625 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 164
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-2355

Programming
with External
Hardware
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
Altera Corporation
SAMPLE/PRELOAD
EXTEST
BYPASS
CLAMP
IDCODE
USERCODE
ISP Instructions
Table 6. MAX 7000B JTAG Instructions
JTAG Instruction
f
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the
boundary-scan test data to pass synchronously through a selected device to adjacent
devices during normal operation.
Allows the values in the boundary-scan register to determine pin states while placing the
1-bit bypass register between the TDI and TDO pins.
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO.
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO.
These instructions are used when programming MAX 7000B devices via the JTAG ports
with the MasterBlaster or ByteBlasterMV download cable, or using a Jam File (.jam),
Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded
processor or test equipment.
MAX 7000B devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
For more information, see the
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see
MAX 7000B devices include the JTAG boundary-scan test circuitry
defined by IEEE Std. 1149.1.
supported by MAX 7000B devices. The pin-out tables starting on
of this data sheet show the location of the JTAG control pins for each
device. If the JTAG interface is not required, the JTAG pins are available
as user I/O pins.
Programming Hardware
MAX 7000B Programmable Logic Device Data Sheet
Description
Table 6
Altera Programming Hardware Data
describes the JTAG instructions
Manufacturers.
Sheet.
page 59
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