EPM570F256C3N Altera, EPM570F256C3N Datasheet - Page 25
![IC MAX II CPLD 570 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM570F256C3N
Manufacturer Part Number
EPM570F256C3N
Description
IC MAX II CPLD 570 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F256C3N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
160
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
No. Of I/o's
160
Propagation Delay
5.4ns
Global Clock Setup Time
1.2ns
Frequency
304MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1312
EPM570F256C3N
EPM570F256C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F256C3N
Manufacturer:
ALTERA21
Quantity:
539
Part Number:
EPM570F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: MAX II Architecture
Global Signals
© October 2008 Altera Corporation
Figure 2–13. Global Clock Generation
Note to
(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.
The global clock network drives to individual LAB column signals, LAB column
clocks [3..0], that span an entire LAB column from the top to the bottom of the device.
Unused global clocks or control signals in a LAB column are turned off at the LAB
column clock buffers shown in
multiplexed down to two LAB clock signals and one LAB clear signal. Other control
signal types route from the global clock network into the LAB local interconnect. See
“LAB Control Signals” on page 2–5
Figure 2–13
:
Logic Array(1)
GCLK0
GCLK1
GCLK2
GCLK3
Figure
for more information.
4
2–14. The LAB column clocks [3..0] are
4
Global Clock
Network
MAX II Device Handbook
2–17