EPM570T144C3N Altera, EPM570T144C3N Datasheet - Page 55
![IC MAX II CPLD 570 LE 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EPM570T144C3N
Manufacturer Part Number
EPM570T144C3N
Description
IC MAX II CPLD 570 LE 144-TQFP
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570T144C3N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
116
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1318
EPM570T144C3N
EPM570T144C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570T144C3N
Manufacturer:
ALTERA
Quantity:
10
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
Figure 4–4. ESD Protection During Negative Voltage Zap
Power-On Reset Circuitry
© October 2008 Altera Corporation
When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V
is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current
path is from GND to the I/O pin, as shown in
MAX II devices have POR circuits to monitor V
power-up. The POR circuit monitors these voltages, triggering download from the
non-volatile configuration flash memory (CFM) block to the SRAM logic, maintaining
tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this
process. When the MAX II device enters user mode, the POR circuit releases the I/O
pins to user functionality. The POR circuit of the MAX II (except MAX IIZ) device
continues to monitor the V
POR circuit of the MAX IIZ device does not monitor the V
device enters into user mode. More details are provided in the following sub-sections.
I/O
GND
Source
Drain
Drain
Source
CCINT
PMOS
NMOS
voltage level to detect a brown-out condition. The
Gate
Gate
P-Substrate
Figure
CCINT
N+
N+
and V
D
S
4–4.
GND
I/O
G
CCIO
CCINT
voltage levels during
voltage level after the
MAX II Device Handbook
4–5