EPM7064AETI44-7N Altera, EPM7064AETI44-7N Datasheet - Page 13
![IC MAX 7000 CPLD 64 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM7064AETI44-7N
Manufacturer Part Number
EPM7064AETI44-7N
Description
IC MAX 7000 CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7064AETI44-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Cpld Type
EEPROM
No. Of Macrocells
64
No. Of I/o's
36
Propagation Delay
7.5ns
Global Clock Setup Time
4.7ns
Frequency
135.1MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2011
EPM7064AETI44-7N
EPM7064AETI44-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7064AETI44-7N
Manufacturer:
ALTERA
Quantity:
20
Company:
Part Number:
EPM7064AETI44-7N
Manufacturer:
ALTERA
Quantity:
37
MAX 7000A Programmable Logic Device Data Sheet
Figure 5. MAX 7000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
13