XC2C64A-5QFG48C Xilinx Inc, XC2C64A-5QFG48C Datasheet - Page 7
![IC CRII CPLD 64MCRCELL 48QFN](/photos/6/70/67087/xc2c64a-5qfg48c_sml.jpg)
XC2C64A-5QFG48C
Manufacturer Part Number
XC2C64A-5QFG48C
Description
IC CRII CPLD 64MCRCELL 48QFN
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C64A-5QFG48C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.6ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1500
Number Of I /o
37
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-QFN
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Package
48QFN EP
Family Name
CoolRunnerÂ-II
Device System Gates
1500
Number Of Macro Cells
64
Maximum Propagation Delay Time
5 ns
Number Of User I/os
37
Number Of Logic Blocks/elements
4
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
263 MHz
Number Of Product Terms Per Macro
40
For Use With
122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Other names
122-1419
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2C64A-5QFG48C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Internal Timing Parameters
DS311 (v2.3) November 19, 2008
Product Specification
Buffer Delays
T
T
T
T
T
T
T
P-term Delays
T
T
T
Macrocell Delay
T
T
T
T
T
T
T
T
Feedback Delays
T
T
I/O Standard Time Adder Delays 1.5V CMOS
T
T
T
I/O Standard Time Adder Delays 1.8V CMOS
T
T
T
AOI
OUT
OEM
OUT15
OUT18
IN
DIN
GCK
GSR
GTS
EN
CT
LOGI1
LOGI2
PDI
SUI
HI
ECSU
ECHO
COI
CDBL
F
HYS15
SLEW15
HYS18
SLEW
Symbol
R
Input buffer delay
Direct data register input delay
Global clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
Control term delay
Single P-term delay adder
Multiple P-term delay adder
Input to output valid
Setup before clock
Hold after clock
Enable clock setup time
Enable clock hold time
Clock to output valid
Set/reset to output valid
Clock doubler delay
Feedback delay
Macrocell to global OE delay
Hysteresis input adder
Output adder
Output slew rate adder
Hysteresis input adder
Output adder
Output slew rate adder
Parameter
(1)
www.xilinx.com
Min.
1.4
0.0
0.9
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Max.
1.7
2.6
1.6
2.4
2.7
1.9
5.3
2.0
0.5
0.4
0.5
0.4
1.7
1.5
1.7
4.0
0.9
4.0
3.0
3.5
0
0
-
-
-
-
XC2C64A CoolRunner-II CPLD
Min.
1.8
0.0
1.3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
2.4
4.0
2.5
3.5
3.9
2.8
6.1
2.5
0.8
0.8
0.7
0.7
2.0
3.0
1.7
6.0
1.5
6.0
4.0
5.0
0
0
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7