EPM9560RC240-15 Altera, EPM9560RC240-15 Datasheet - Page 30

• Manufacturer Part Number: EPM9560RC240-15
• Description: IC MAX 9000 CPLD 560 240-RQFP
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9560RC240-15

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 35
• Number Of Macrocells: 560
• Number Of Gates: 12000
• Number Of I /o: 191
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 240-RQFP
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 35
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-2366

MAX 9000 Programmable Logic Device Family Data Sheet
30
Timing Model
f
The continuous, high-performance FastTrack Interconnect ensures
predictable performance and accurate simulation and timing analysis.
This predictable performance contrasts with that of FPGAs, which use a
segmented connection scheme and hence have unpredictable
performance. Timing simulation and delay prediction are available with
the MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time prediction, and
device-wide performance analysis.
The MAX 9000 timing model in
correspond to various paths and functions in the circuit. This model
contains three distinct parts: the macrocell, IOC, and interconnect,
including the row and column FastTrack Interconnect and LAB local array
paths. Each parameter shown in
value in the internal timing characteristics tables in this data sheet. Hand-
calculations that use the MAX 9000 timing model and these timing
parameters can be used to estimate MAX 9000 device performance.
For more information on calculating MAX 9000 timing delays, see
Application Note 77 (Understanding MAX 9000
Figure 14
Figure 14
shows the delays that
is expressed as a worst-case
Timing).
Altera Corporation