EPM7512AEQC208-7 Altera, EPM7512AEQC208-7 Datasheet - Page 37
![IC MAX 7000 CPLD 512 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPM7512AEQC208-7
Manufacturer Part Number
EPM7512AEQC208-7
Description
IC MAX 7000 CPLD 512 208-PQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7512AEQC208-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
176
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Family Name
MAX 7000A
# Macrocells
512
Number Of Usable Gates
10000
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
32
# I/os (max)
176
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2359
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7512AEQC208-7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7512AEQC208-7N
Manufacturer:
ALTERA
Quantity:
174
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 19. EPM7064AE External Timing Parameters
Input to non-
registered output
I/O input to non-
registered output
Global clock setup
time
Global clock hold time
Global clock setup
time of fast input
Global clock hold time
of fast input
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width
for clear and preset
Minimum global clock
period
Maximum internal
global clock frequency
Minimum array clock
period
Maximum internal
array clock frequency
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
222.2
222.2
Min
2.8
0.0
2.5
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
-4
MAX 7000A Programmable Logic Device Data Sheet
Note (1)
Max
4.5
4.5
3.1
4.3
4.5
4.5
135.1
135.1
Speed Grade
Min
4.7
0.0
3.0
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
3.0
-7
Max
7.5
7.5
5.1
7.2
7.4
7.4
100.0
100.0
Min
6.2
0.0
3.0
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
4.0
-10
Max
10.0
10.0
10.0
10.0
7.0
9.6
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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