EPM3064ATC100-4 Altera, EPM3064ATC100-4 Datasheet - Page 16
![IC MAX 3000A CPLD 64 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EPM3064ATC100-4
Manufacturer Part Number
EPM3064ATC100-4
Description
IC MAX 3000A CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3064ATC100-4
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
66
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Family Name
MAX 3000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
250MHz
Propagation Delay Time
4.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
66
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1157
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3064ATC100-4
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EPM3064ATC100-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM3064ATC100-4N
Manufacturer:
ALTERA
Quantity:
1 600
MAX 3000A Programmable Logic Device Family Data Sheet
16
Table 4. MAX 3000A t
Table 5. MAX 3000A In-System Programming Times for Different Test Clock Frequencies
Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Device
Device
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Device
10 MHz
10 MHz
2.01
2.01
2.02
2.05
2.09
0.00
0.01
0.01
0.02
0.03
PULSE
5 MHz
5 MHz
The programming times described in
with the worst-case method using the enhanced ISP algorithm.
Tables 5
verification times for several common test clock frequencies.
& Cycle
2.01
2.02
2.04
2.09
2.18
0.01
0.01
0.02
0.03
0.06
t
PPULSE
2.00
2.00
2.00
2.00
2.00
TCK
and
2 MHz
2 MHz
2.03
2.05
2.10
2.23
2.45
0.01
0.02
0.04
0.08
0.15
(s)
Values
Programming
6
show the in-system programming and stand alone
1 MHz
1 MHz
2.06
2.11
2.21
2.45
2.89
0.02
0.04
0.07
0.15
0.30
Cycle
105,000
205,000
447,000
890,000
55,000
f
f
TCK
TCK
PTCK
500 kHz
500 kHz
2.11
2.21
2.41
2.90
3.78
0.04
0.07
0.14
0.30
0.60
200 kHz
Tables 4
200 kHz
2.28
2.53
3.03
4.24
6.45
0.09
0.18
0.34
0.75
1.49
t
VPULSE
0.002
0.002
0.002
0.002
0.002
Stand-Alone Verification
through
(s)
100 kHz
100 kHz
10.90
0.18
0.35
0.68
1.49
2.97
2.55
3.05
4.05
6.47
6
Altera Corporation
are associated
50 kHz
50 kHz
10.94
19.80
0.36
0.70
1.36
2.98
5.94
Cycle
3.10
4.10
6.10
149,000
297,000
18,000
35,000
68,000
VTCK
Units
Units
s
s
s
s
s
s
s
s
s
s