EPM3064ATC44-7 Altera, EPM3064ATC44-7 Datasheet - Page 29
![IC MAX 3000A CPLD 64 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM3064ATC44-7
Manufacturer Part Number
EPM3064ATC44-7
Description
IC MAX 3000A CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3064ATC44-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1161
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3064ATC44-7
Manufacturer:
ALTERA
Quantity:
1
Part Number:
EPM3064ATC44-7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM3064ATC44-7/144-10S
Manufacturer:
ALTERA
Quantity:
6 220
Company:
Part Number:
EPM3064ATC44-7/I44-10
Manufacturer:
ALTERA
Quantity:
71
Company:
Part Number:
EPM3064ATC44-7/I44-10
Manufacturer:
LINEAR
Quantity:
1 770
Part Number:
EPM3064ATC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM3064ATC44-7N/I44-10N
Manufacturer:
ALTERA
Quantity:
38
Part Number:
EPM3064ATC44-7N/I44-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
IN
IO
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
RD
COMB
IC
EN
GLOB
PRE
CLR
Table 17. EPM3032A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
MAX 3000A Programmable Logic Device Family Data Sheet
Min
1.3
0.6
–4
Max
0.7
0.7
1.9
0.5
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
1.2
0.6
0.8
1.2
1.2
Note (1)
Speed Grade
Min
2.0
1.0
–7
Max
1.2
1.2
3.1
0.8
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
1.0
2.0
1.0
1.3
1.9
1.9
Min
2.8
1.3
–10
Max
10.0
1.5
1.0
3.3
5.0
1.3
2.5
1.9
2.6
1.5
4.0
1.2
0.0
1.8
2.3
6.8
5.0
5.5
1.5
1.2
2.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29