ATF1508ASL-20JC84 Atmel, ATF1508ASL-20JC84 Datasheet - Page 13

• Manufacturer Part Number: ATF1508ASL-20JC84
• Description: IC CPLD 128 MACROCELL LP 84PLCC
• Manufacturer: Atmel
• Series: ATF1508AS(L)r

Specifications of ATF1508ASL-20JC84

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 20.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 128
• Number Of I /o: 64
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 5V
• Memory Type: EEPROM
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

Power-down
Mode
Power-down AC Characteristics
Notes:
Absolute Maximum Ratings*
0784P–PLD–7/05
t
t
t
t
t
t
t
t
t
t
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
Symbol
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
1. For slow slew outputs, add t
2. Pin or product term.
Valid I, I/O before PD High
Valid OE
Valid Clock
I, I/O Don’t Care after PD High
OE
Clock
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
(2)
Don’t Care after PD High
(2)
Don’t Care after PD High
(2)
(2)
before PD High
Parameter
before PD High
The ATF1508AS includes two pins for optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high,
the device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched and held. Therefore, all registered and combinatorial out-
put data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-
Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O
hold latches remain active to ensure that pins do not float to indeterminate levels, further
reducing system power. The power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD pin logic array input. However, bur-
ied logic resources in this macrocell may still be used.
SSO
.
(1)(2)
Min
7
7
7
-7
(1)
(1)
(1)
Max
12
12
12
1
1
1
1
Min
10
10
10
*NOTICE:
Note:
-10
Max
15
15
15
1
1
1
1
1. Minimum voltage is -0.6V DC, which may under-
Min
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.
15
15
15
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
-15
Max
25
25
25
1
1
1
1
Min
20
20
20
-20
ATF1508AS(L)
Max
30
30
30
1
1
1
1
Min
25
25
25
-25
CC
Max
+ 0.75V DC,
35
35
35
1
1
1
1
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
13