ATF1502ASV-15JU44 Atmel, ATF1502ASV-15JU44 Datasheet - Page 9

• Manufacturer Part Number: ATF1502ASV-15JU44
• Description: IC CPLD EE HP 15NS 44-PLCC
• Manufacturer: Atmel
• Series: ATF1502ASVr

Specifications of ATF1502ASV-15JU44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Family Name: ATF1502ASV
• # Macrocells: 32
• Number Of Usable Gates: 750
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 32
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant

7.2
1615J–PLD–01/06
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typi-
cal BSC consists of three capture registers or scan registers and up to two update registers.
There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in
the device are chained together through the capture registers. Input to the capture register chain
is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used
to capture active device data signals, to shift data in and out of the device and to load data into
the update registers. Control signals are generated internally by the JTAG TAP controller. The
BSC configuration for the input and I/O pins and macrocells is shown below.
Figure 7-1.
Note:
The ATF1502ASV has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
Dedicated
Input
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
To Internal
Logic
(From Next Register)
TDI
SHIFT
CLOCK
Registers
Capture
ATF1502ASV
TDO
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