ATF1502ASV-15AU44 Atmel, ATF1502ASV-15AU44 Datasheet - Page 14

• Manufacturer Part Number: ATF1502ASV-15AU44
• Description: IC CPLD EE HP 15NS 44-TQFP
• Manufacturer: Atmel
• Series: ATF1502ASVr

Specifications of ATF1502ASV-15AU44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 32
• Number Of I /o: 32
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Family Name: ATF1502ASV
• # Macrocells: 32
• Number Of Usable Gates: 750
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 32
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant

13. AC Characteristics
Table 13-1.
14
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
t
t
t
t
t
t
t
t
t
t
t
PD1
PD2
SU
H
FSU
FH
COP
CH
CL
ASU
AH
ACOP
ACH
ACL
CNT
CNT
ACNT
ACNT
MAX
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
ZX1
ZX2
ATF1502ASV
Parameter
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
Global Clock Hold Time
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
Logic Control Delay
Internal Output Enable Delay
Output Buffer and Pad Delay
(Slow slew rate = OFF;
V
Output Buffer Enable Delay
(Slow slew rate = OFF;
V
Output Buffer Enable Delay
(Slow slew rate = OFF;
V
AC Characteristics
CC
CCIO
CCIO
= 3.3V; C
= 5.0V; C
= 3.3V; C
L
= 35 pF)
L
L
= 35 pF)
= 35 pF)
(1)
76.9
76.9
Min
100
11
3
3
0
3
1
5
5
4
4
6
6
-15
Max
15
12
15
13
13
8
2
2
2
8
1
6
6
3
5
7
7
83.3
Min
1.5
16
66
66
0
3
6
6
4
5
8
8
-20
Max
20
16
10
20
16
16
10
2
2
7
7
3
2
1
5
9
9
1615J–PLD–01/06
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns