AD5764ASU-REEL7 Analog Devices Inc, AD5764ASU-REEL7 Datasheet - Page 21

• Manufacturer Part Number: AD5764ASU-REEL7
• Description: IC DAC 16BIT QUAD VOUT 32TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5764ASU-REEL7

• Design Resources: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006)
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 275mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2
0
0
0
0
Table 12. Explanation of Function Register Options
Option
NOP
Local Ground Offset Adjust
D0/D1 Direction
D0/D1 Value
SDO Disable
Clear
Load
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 10). The data bits are in Position DB15 to Position DB0, as shown in Table 13.
Table 13. Programming the Data Register Bit Map
REG2
0
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each
DAC, as shown in Table 14 and Table 15.
Table 14. Programming the Coarse Gain Register Bit Map
REG2
0
Table 15. Output Range Selection
Output Range
±10 V (Default)
±10.2564 V
±10.5263 V
REG1
0
0
0
0
REG1
1
REG1
1
REG0
0
0
0
0
0
0
1
1
A2
0
0
0
0
A1
REG0
1
Description
No operation instruction used in readback operations.
Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local
ground offset adjust function (default). Refer to the Design Features section for further details.
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer
to the Design Features section for further details.
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1
pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is
active as an input. When enabled as inputs, these bits are don’t cares during a write operation.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in
binary mode.
Addressing this function updates the data register and consequently the analog outputs.
REG0
0
0
1
0
1
A0
DB15:DB6
Don’t care
A2
A2
DB5
Local ground
offset adjust
DAC address
DAC address
A1
A1
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A0
A0
CG1
0
0
1
DB4
D1 direction
Clear, data = don’t care
Load, data = don’t care
NOP, data = don’t care
DB3
D1 value
DB15: DB2
Don’t care
DB2
D0 direction
16-bit DAC data
DB15:DB0
DB1
CG1
CG0
0
1
0
DB1
D0 value
AD5764
DB0
SDO disable
DB0
CG0