AD5382BST-3 Analog Devices Inc, AD5382BST-3 Datasheet - Page 22
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AD5382BST-3
Manufacturer Part Number
AD5382BST-3
Description
IC DAC 14BIT 32CH 3V 100-LQFP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5382BSTZ-5.pdf
(40 pages)
Specifications of AD5382BST-3
Design Resources
32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012)
Settling Time
8µs
Number Of Bits
14
Data Interface
Serial, Parallel
Number Of Converters
32
Voltage Supply Source
Single Supply
Power Dissipation (max)
65mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
For Use With
EVAL-AD5382EB - BOARD EVAL FOR AD5382
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD5382
Table 14. Gain Data Format (REG1 = 0, REG0 = 1)
11
10
01
00
00
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5382 contains a number of special function registers
(SFRs), as outlined in Table 15. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bits A4 to A0.
Table 15. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
X
0
0
0
0
0
1
0
0
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, A4–A0 = 00000
Performs no operation but is useful in serial readback mode to
clock out data on D
low during a NOP operation.
Write Clear Code
REG1 = REG0 = 0, A4–A0 = 00001
DB13–DB0 = Contain the clear code data
Bringing the CLR line low or exercising the soft clear function
loads the contents of the DAC registers with the data contained
in the user-configurable Clear register, and sets VOUT0 to
VOUT31 accordingly. This can be very useful for setting up a
specific output voltage in a clear condition. It is also beneficial
for calibration purposes; the user can load full scale or zero
scale to the clear code register and then issue a hard-ware or
software clear to load this code to all DACs, removing the
need for individual writes to each DAC. Default on power-up
is all zeros.
A4
0
0
0
0
0
0
0
0
0
1111
1111
1111
0111
0000
DB13 to DB0
A3
0
0
0
1
1
1
1
1
1
1111
1111
1111
1111
0000
OUT
A2
0
0
0
0
0
1
1
0
1
for diagnostic purposes. BUSY pulses
1110
1110
1110
1110
0000
A1
0
0
1
0
0
0
0
1
1
A0
0
1
0
0
1
0
0
0
1
Gain Factor
1
0.75
0.5
0.25
0
Function
NOP (No Operation)
Write Clear Code
Soft Clear
Soft Power-Down
Soft Power-Up
Control Register Write
Control Register Read
Monitor Channel
Soft Reset
Rev. B | Page 22 of 40
Soft Clear
REG1 = REG0 = 0, A4–A0 = 00010
DB13–DB0 = Don’t Care
Executing this instruction performs a software clear, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the Clear Code.
register (
and is indicated by the
Soft Power-Down
REG1 = REG0 = 0, A4–A0 = 01000
DB13–DB0 = Don’t Care
Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 μA max and the digi-
tal current to 20 μA max. In power-down mode, the output
amplifier can be configured as a high impedance output or
provide a 100 kΩ load to ground. The contents of all internal
registers are retained in power-down mode. No register can
be written to while in power-down.
Soft Power-Up
REG1 = REG0 = 0, A4–A0 = 01001
DB13–DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power-down is 8 μs.
The hardware power-down and software functions are
internally combined in a digital OR function.
Soft RESET
REG1 = REG0 = 0, A4–A0 = 01111
DB13–DB0 = Don’t Care
This instruction is used to implement a software reset.
All internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of
the DAC registers are cleared, setting all analog outputs to 0 V.
The soft reset activation time is 135 μs max.
Table 15
). It takes 35 μs to fully execute the Soft Clear
BUSY low time.