AD9763AST Analog Devices Inc, AD9763AST Datasheet
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AD9763AST
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AD9763AST Summary of contents
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FEATURES 10-/12-/14-bit dual transmit digital-to-analog converters (DACs) 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control Dual-port or interleaved data On-chip 1.2 V ...
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AD9763/AD9765/AD9767 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Dynamic Specifications ............................................................... 6 Digital Specifications ...
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REVISION HISTORY Revision History: AD9763/AD9765/AD9767 6/09—Rev Rev. F Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91, Deleted Original Figure 91 to Figure 94 ....................................... 34 1/08—Revision E: Initial Combined Version Revision History: AD9763 1/08—Rev. ...
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AD9763/AD9765/AD9767 Revision History: AD9767 1/08—Rev Rev. E Combined with AD9763 and AD9765 Data Sheets ....... Universal Changes to Figure 1 .......................................................................... 1 Changes to Features Section............................................................ 1 Changes to Applications Section .................................................... 1 Changes to Timing Diagram Section ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL 25°C ...
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AD9763/AD9765/AD9767 DYNAMIC SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate ...
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DIGITAL SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V ...
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AD9763/AD9765/AD9767 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To AVDD ACOM DVDD1, DVDD2 DCOM1/DCOM2 ACOM DCOM1/DCOM2 AVDD DVDD1/DVDD2 MODE, DCOM1/DCOM2 CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL Digital Inputs DCOM1/DCOM2 ACOM OUTA1 OUTA2 I /I OUTB1 OUTB2 REFIO, FSADJ1, ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB9P1 (MSB) 1 PIN 1 DB8P1 2 DB7P1 3 DB6P1 4 DB5P1 5 AD9763 DB4P1 6 TOP VIEW (Not to Scale) DB3P1 7 ...
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AD9763/AD9765/AD9767 Table 6. Pin Function Descriptions Pin No. AD9763 AD9765 AD9767 14, 13, 14, N 35, 36 15, 21 15, 21 15, 21 16, 22 16, ...
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TYPICAL PERFORMANCE CHARACTERISTICS AD9763 AVDD = 3 DVDD = 3 unless otherwise noted 5MSPS CLK f = 25MSPS CLK 65MSPS CLK (MHz) ...
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AD9763/AD9765/AD9767 85 910kHz/10MSPS 80 2.27MHz/25MSPS 75 70 5.91MHz/65MSPS 65 60 –20 –16 –12 –8 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 85 5MHz/25MSPS 80 1MHz/5MSPS 75 2MHz/10MSPS 70 65 13MHz/65MSPS 60 55 –20 –16 –12 –8 A ...
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OUT f = 10MHz OUT 25MHz OUT 40MHz OUT 60MHz OUT 45 –60 –40 – TEMPERATURE (°C) Figure 18. SFDR vs. Temperature @ ...
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AD9763/AD9765/AD9767 AD9765 AVDD = 3 DVDD = 3 Nyquist, unless otherwise noted 5MSPS CLK f = 25MSPS CLK 65MSPS CLK ...
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Figure 29. Single-Tone SFDR vs OUT OUT 90 1MHz/5MSPS 85 2MHz/10MSPS 5MHz/25MSPS 13MHz/65MSPS 65 25MHz/125MSPS 60 55 –20 –15 –10 –5 A (dBFS) OUT Figure 30. Single-Tone SFDR ...
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AD9763/AD9765/AD9767 1MHz OUT 10MHz OUT 25MHz OUT 40MHz 60 OUT 60MHz OUT 50 45 –60 –40 – TEMPERATURE (°C) Figure 35. ...
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AD9767 AVDD = 3 DVDD = 3 Nyquist, unless otherwise noted 5MSPS CLK f = 25MSPS CLK 80 f CLK 65MSPS CLK 50 1 ...
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AD9763/AD9765/AD9767 90 910kHz/10MSPS 85 2.27MHz/25MSPS 11.37MHz/125MSPS 65 5.91MHz/65MSPS Figure 46. Single-Tone SFDR vs. A OUT 90 1MHz/5MSPS 85 2MHz/10MSPS 80 75 5MHz/25MSPS 70 65 13MHz/65MSPS –20 –15 –10 A (dBFS) OUT Figure 47. Single-Tone ...
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OUT 10MHz OUT 25MHz OUT 40MHz OUT 60MHz OUT 50 45 –60 –40 – TEMPERATURE (°C) Figure 52. SFDR ...
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AD9763/AD9765/AD9767 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL ...
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THEORY OF OPERATION FSADJ1 R 1 SET REFIO 2kΩ 0.1µF FSADJ2 R 2 SET 2kΩ 1.2V REF WRT1/ GAINCTRL IQWRT DVDD1/DVDD2 50Ω DCOM1/DCOM2 RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767, Testing ...
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AD9763/AD9765/AD9767 The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from via an external network connected to the full scale adjust (FSADJ) pin. The external network, ...
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DAC TRANSFER FUNCTION Both DACs in the AD9763/AD9765/AD9767 provide comple- mentary current outputs, I and I OUTA OUTB full-scale current output (I ) when all bits are high (that is, OUTFS DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/ AD9767, respectively), ...
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AD9763/AD9765/AD9767 I and I also have a negative and positive voltage OUTA OUTB compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of −1 set by the breakdown limits ...
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Interleaved Mode Timing When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767 operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET. ...
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AD9763/AD9765/AD9767 Because the AD9763/AD9765/AD9767 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9763/AD9765/AD9767 with reduced logic swings and a corresponding digital ...
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I OUTFS Figure 69. I vs. I AVDD OUTFS 35 30 125MSPS 25 100MSPS 20 65MSPS 15 10 25MSPS 5 5MSPS 0 0 0.1 0.2 0 ...
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AD9763/AD9765/AD9767 APPLYING THE AD9763/AD9765/AD9767 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9763/AD9765/AD9767, with I 20 mA, unless otherwise noted. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output ...
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I OUTA 225Ω AD9763/ AD9765/ AD9767 225Ω I OUTB C OPT 25Ω 25Ω Figure 74. Single-Supply DC Differential-Coupled Circuit SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT Figure 75 shows the AD9763/AD9765/AD9767 configured to provide a unipolar output range of approximately ...
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AD9763/AD9765/AD9767 Note that the data in Figure 77 is given in terms of current out vs. voltage in. Noise on the analog power supply has the effect of modulating the internal current sources and therefore the output current. The voltage ...
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APPLICATIONS VDSL EXAMPLE APPLICATIONS USING THE AD9765 AND AD9767 Very high frequency digital subscriber line (VDSL) technology is growing rapidly in applications requiring data transfer over relatively short distances. By using quadrature amplitude modulation (QAM) and transmitting the data in ...
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AD9763/AD9765/AD9767 QUADRATURE AMPLITUDE MODULATION (QAM) EXAMPLE USING THE AD9763 QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (that is, CDMA) ...
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I and Q digital data can be fed into the AD9763 in two ways. In dual-port mode, the digital I information drives one input port, and the digital Q information drives the other input port interpolation filter precedes ...
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AD9763/AD9765/AD9767 EVALUATION BOARD GENERAL DESCRIPTION The AD9763/AD9765/AD9767-EBZ is an evaluation board for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9763/AD9765/AD9767 in ...
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CC0805 CC0805 Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (2) Rev Page AD9763/AD9765/AD9767 RC0603 RC0805 RC0805 RC0805 RC0805 RC0805 00617-091 ...
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AD9763/AD9765/AD9767 L6 O2N LC0805 CC0805 C24 L5 DNP O2P LC0805 AVDD2 C20 CC0603 10UF BCASE C27 10V 100PF 2 L4 O1N LC0805 DNP CC0805 O1P LC0805 DNP R23 51 C31 RC0603 D N ...
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RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 89. Digital Input Signaling (1) Rev Page AD9763/AD9765/AD9767 00617-093 ...
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AD9763/AD9765/AD9767 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 90. Digital Input Signaling (2) Rev Page 00617-087 ...
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CC0805 CC0805 RC07CUP RC0805 RC0805 Figure 91. Device Under Test/Analog Output Signal Conditioning Rev Page AD9763/AD9765/AD9767 RC07CUP RC0805 RC0805 00617-088 ...
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AD9763/AD9765/AD9767 EVALUATION BOARD LAYOUT Figure 92. Assembly, Top Side Rev Page ...
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Figure 93. Assembly, Bottom Side Rev Page AD9763/AD9765/AD9767 ...
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... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD9763ASTZ –40°C to +85°C 1 AD9763ASTZRL –40°C to +85°C AD9765AST –40°C to +85°C AD9765ASTRL –40°C to +85°C AD9765ASTZ 1 –40°C to +85°C 1 AD9765ASTZRL –40°C to +85°C ...
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NOTES AD9763/AD9765/AD9767 Rev Page ...
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AD9763/AD9765/AD9767 NOTES ©1999-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00617-0-6/09(F) Rev Page ...