MAX5150ACPE+ Maxim Integrated Products, MAX5150ACPE+ Datasheet - Page 11

• Manufacturer Part Number: MAX5150ACPE+
• Description: IC DAC 13BIT DUAL LP SER 16-DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5150ACPE+

• Settling Time: 16µs
• Number Of Bits: 13
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
Figure 5. Serial-Interface Timing Diagram
MSB ..................................................................................LSB
Address Bits
1 Address/2 Control Bits
Low-Power, Dual, 13-Bit Voltage-Output DACs
A0
MAX5150
MAX5151
SCLK
DIN
CS
Control Bits
SCLK
______________________________________________________________________________________
C1, C0
DIN
16 Bits of Serial Data
CS
A0
1
C1
MSB.......Data Bits.........LSB
D12.................................D0
C0 D12 D11 D10 D9
CPOL = 0, CPHA = 0
MOSI
SCK
I/O
13 Data Bits
SPI/QSPI
PORT
+5V
SS
D8
8
D7
The address and control bits determine the MAX5150/
MAX5151's response, as outlined in Table 1.
The MAX5150/MAX5151's digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
The 16-bit data can be sent as two 8-bit packets (SPI,
Microwire), with CS low during this period. The address
and control bits determine which register will be updat-
ed, and the state of the registers when exiting shut-
down. The 3-bit address/control determines the
following:
• registers to be updated
• clock edge on which data is to be clocked out via
• state of the user-programmable logic output
• configuration of the device after shutdown.
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
9
the serial-data output (DOUT)
D6
with Serial Interface
D5
D4
D3
D2
D1
D0
16
COMMAND
EXECUTED
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