88PG8226A1-NFE1C000 Marvell, 88PG8226A1-NFE1C000 Datasheet - Page 12

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88PG8226A1-NFE1C000

Manufacturer Part Number
88PG8226A1-NFE1C000
Description
Manufacturer
Marvell
1.2
1.2.1
Table 2:
Table 3:
Doc. No. MV-S103563-00 Rev. C
Page 12
Pi n Typ e
I
O
S
NC
GND
Pi n #
1
2
3
4
5
P in N a m e
EN
SFB2
SVIN
SGND
SFB1
Pin Type Definitions
Pin Descriptions
Pin Description
Pin Types
Table 3 provides pin descriptions for the 88PG82XX.
88PG82XX
Datasheet
Pi n Typ e
I
I
S
GND
I
D e f in it io n
Input Only
Output Only
Supply
Not Connected
Ground
Document Classification: Proprietary Information
P i n D es c r ip t i o n
Enable.
Logic high (> 2.0V) enables both switching regulators. Logic low (<0.8V)
disables the regulators. When disabled, the switch nodes SW1 and SW2 are
Hi-Z. The feedback nodes SFB1 and SFB2 are pulled down by 20K resistors,
and the power on reset nodes POR1 and POR2 are pulled down by internal
open drain NFETs. The low signal has to be at least 20 µs to disable both
regulators. If this pin is left floating, an internal 10 µA current source pulls this
pin high to SVIN, enabling the regulator.
Switching Regulator Feedback.
Senses the output voltage of the switching regulator 2.
Signal Input Voltage.
The input voltage is 2.75V to 5.5V for internal circuitry. Connect a 0.1 µF
decoupling capacitor between SVIN and SGND and position it as close as
possible to the IC.
Ground.
Connect to a ground plane.
Switching Regulator Feedback.
Senses the output voltage of the switching regulator 1.
Copyright © 2008 Marvell
April 23, 2008, 2.00

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