MAX521ACAG+ Maxim Integrated Products, MAX521ACAG+ Datasheet - Page 10

• Manufacturer Part Number: MAX521ACAG+
• Description: IC DAC 8BIT OCTAL R-R 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX521ACAG+

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: I²C, Serial
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 640mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Number Of Dac Outputs: 8
• Resolution: 8 bit
• Interface Type: Serial (I2C)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 10 mA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX520/MAX521 use a simple 2-wire serial interface
requiring only two I/O lines (2-wire bus) of a standard
microprocessor (µP) port. Figure 1 shows the timing dia-
gram for signals on the 2-wire bus. Figure 2 shows the
typical application of the MAX520/MAX521. The 2-wire
bus can have several devices (in addition to the
MAX520/MAX521) attached. The two bus lines (SDA and
SCL) must be high when the bus is not in use. When in
use, the port bits are toggled to generate the appropriate
signals for SDA and SCL. External pull-up resistors are
not required on these lines. The MAX520/MAX521 can
be used in applications where pull-up resistors are
required (such as in I
ity with the existing circuitry.
The MAX520/MAX521 are receive-only devices and
must be controlled by a bus master device. They oper-
ate at SCL rates up to 400kHz. A master device sends
information to the devices by transmitting their address
over the bus and then transmitting the desired informa-
tion. Each transmission consists of a START condition,
the MAX520/MAX521’s programmable slave-address,
one or more command-byte/output-byte pairs (or a
command byte alone, if it is the last byte in the trans-
mission), and finally, a STOP condition (Figure 3).
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low. SDA’s state is sampled, and therefore must
remain stable while SCL is high. The only exceptions to
this are the START and STOP conditions. Data is transmit-
ted in 8-bit bytes. Nine clock cycles are required to trans-
fer the data bits to the MAX520/MAX521. Set SDA low
during the 9th clock cycle as the MAX520/MAX521 pull
SDA low during this time. R
that flows during this time if SDA stays high for short peri-
ods of time.
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
Figure 3. A Complete Serial Transmission
10
_______________Detailed Description
SDA
______________________________________________________________________________________
SCL
START CONDITION
MSB
SLAVE ADDRESS BYTE
2
C systems) to maintain compatibil-
C
(Figure 2) limits the current
LSB
Serial Interface
ACK
MSB
COMMAND BYTE
Figure 2. Typical Application Circuit
R
1k
LSB
C
SDA
C
+5V
SCL
ACK
SCL
SDA
AD0
AD1
AD2
SCL
SDA
AD0
AD1
MAX520
MAX521
MSB
OCTAL
QUAD
DAC
DAC
OUTPUT BYTE
OUT0
OUT1
OUT2
OUT3
OUT0
OUT1
OUT2
OUT6
OUT7
REF0
REF1
REF2
REF3
REF0
REF4
.
.
.
.
.
.
.
+5V
+1V
+4V
+5V
OFFSET ADJUSTMENT
OFFSET ADJUSTMENT
GAIN ADJUSTMENT
GAIN ADJUSTMENT
BRIGHTNESS ADJUSTMENT
CONTRAST ADJUSTMENT
LSB
THRESHOLD
ADJUSTMENTS
+5V
ACK
STOP CONDITION
+12V
MOTOR