MAX509BCAP+ Maxim Integrated Products, MAX509BCAP+ Datasheet - Page 10
![IC DAC 8BIT QUAD R-R 20-SSOP](/photos/1/39/13938/175-20-ssop_sml.jpg)
MAX509BCAP+
Manufacturer Part Number
MAX509BCAP+
Description
IC DAC 8BIT QUAD R-R 20-SSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX510BCWE.pdf
(22 pages)
Specifications of MAX509BCAP+
Settling Time
6µs
Number Of Bits
8
Data Interface
Serial
Number Of Converters
4
Voltage Supply Source
Dual ±
Power Dissipation (max)
800mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands
10
A1
0
0
1
1
0
0
1
1
X
X
0
1
1
______________________________________________________________________________________
NOTE: TIMING SPECIFICATION t
SCLK
CS
DIN
DOUT
LDAC
A0
0
1
0
1
0
1
0
1
0
1
X
1
0
12-Bit Serial Word
C1
t
0
0
0
0
1
1
1
1
0
0
1
1
1
CSH0
CLL
IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
t
CSS
C0
1
1
1
1
1
1
1
1
0
0
0
0
0
t
DS
t
DH
D7 . . . . . . . . D0
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
t
CH
t
DO
t
CL
LDAC
1
1
1
1
1
1
1
1
X
X
X
X
X
• • •
• • •
• • •
• • •
• • •
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
Update all DACs from shift register.
No Operation (NOP), shifts data in shift register.
“LDAC” Command, all DACs updated from respective
input registers.
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
t
CSH1
t
CSH2
Function
t
CLL
t
LDW