LC51024MV-52F484C Lattice, LC51024MV-52F484C Datasheet - Page 74
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LC51024MV-52F484C
Manufacturer Part Number
LC51024MV-52F484C
Description
Manufacturer
Lattice
Datasheet
1.LC51024MV-52F484C.pdf
(92 pages)
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Lattice Semiconductor
ispXPLD 5768MX Logic Signal Connections (Continued)
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
sysIO Bank LVDS Pair
0
0
126N
126P
Primary Macrocell/
Function
S26
S24
Macrocell 1
S13
S12
Alternate Outputs
74
Macrocell 2
-
-
ispXPLD 5000MX Family Data Sheet
Alternate
Inputs
S27
S25
Ball Number
256 fpBGA
—
—
Ball Number
484 fpBGA
C4
D5
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