MT90820AP1 Zarlink, MT90820AP1 Datasheet - Page 10

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MT90820AP1

Manufacturer Part Number
MT90820AP1
Description
PB FREE LARGE DIGITAL SWITCH
Manufacturer
Zarlink
Datasheets
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the V/C bit of the
connection memory.
Variable Delay Mode (V/C bit = 0)
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The minimum delay achievable in the MT90820 is three time-slots. When
the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following
frame (channel n, frame p+1). The same frame delay occurs if the input channel n is switched to output channel
n+1 or n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for the MT90820 in the variable delay mode.
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory
buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2.
In the MT90820, the minimum throughput delay achievable in the constant delay mode will be one frame. For
example, in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-
slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3.
Microprocessor Interface
The MT90820 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed and multiplexed buses.
If the IM pin is low, the MT90820 microprocessor interface assumes Motorola non-multiplexed bus mode. If the IM
pin is high, the device micro-processor interface accepts two different timing modes (mode1 and mode2) which
allows direct connection to multiplexed microprocessors.
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
128 - (n-m) time-slots
32 - (n-m) time-slots
64 - (n-m) time-slots
Table 3 - Constant Throughput Delay Value
Table 2 - Variable Throughput Delay Value
m < n
Zarlink Semiconductor Inc.
Delay for Variable Throughput Delay Mode
MT90820
10
(m - output channel number)
(n - input channel number))
m-n + 128 time-slots
m-n + 32 time-slots
m-n + 64 time-slots
m = n, n+1, n+2
Delay for Constant Throughput Delay Mode
128 + (128 - n) + (m- 1) time-slots
32 + (32 - n) + (m - 1) time-slots
64 + (64 - n) + (m- 1) time-slots
(m - output channel number)
(n - input channel number))
m-n time-slots
m-n time-slots
m-n time-slots
m > n+2
Data Sheet

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