M5M5256DVP-70XG Renesas Electronics America, M5M5256DVP-70XG Datasheet - Page 2

• Manufacturer Part Number: M5M5256DVP-70XG
• Manufacturer: Renesas Electronics America

determined by a combination of the dev ice control inputs
/S, /W and /OE. Each mode is summarized in the f unction
table.
ov erlaps with the low lev el /S. The address must be set
up bef ore the write cy cle and must be stable during the
entire cy cle. The data is latched into a cell on the trailing
edge of /W, /S, whichev er occurs f irst, requiring the set-
up and hold time relativ e to these edge to be maintained.
The output enable /OE directly controls the output stage.
Setting the /OE at a high lev el,the output stage is in a
high-impedance state, and the data bus contention
problem in the write cy cle is eliminated.
FUNCTION TABLE
BLOCK DIAGRAM
The operation mode of the M5M5256DFP,VP is
A write cy cle is executed whenev er the low lev el /W
WRITE CONTROL
CHIP SELECT
OUTPUT ENABLE
ADDRESS
INPUT
INPUT
INPUT
INPUT
Note • "H" and "L" in this table mean VIH and VIL, respectiv ely .
/S
H
L
L
L
A 8
A 13
A 14
A 12
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
A 10
A 11
A 9
/W
/S
/OE
/W /OE
• "X" in this table should be "H" or "L".
20
22
10
21
23
24
27
X
L
H
H
25
26
1
2
2
3
4
5
6
7
8
9
X
X
L
H
Non selection
Mode
Read
Write
M5M5256DFP,VP -70G,-70GI,-70XG
(512 ROWS X
32768 WORD
512 COLUMNS)
GENERATOR
High-impedance
High-impedance
CLOCK
X 8BIT
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
D
D
DQ
IN
OUT
and /OE at a low lev el while /S are in an activ e state.
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specif ied
as Icc3 or Icc4, and the memory data can be held at
+2V power supply , enabling battery back-up operation
during power f ailure or power-down operation in the non-
selected mode.
A read cy cle is executed by setting /W at a high lev el
When setting /S at a high lev el, the chip is in a non-
Stand-by
Activ e
Activ e
Activ e
Icc
11
12
13
15
16
17
18
19
28
14
RENESAS LSIs
VCC
GND
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
(5V)
(0V)
DATA I/O
2