MAX509BCAP Maxim Integrated Products, MAX509BCAP Datasheet - Page 12

• Manufacturer Part Number: MAX509BCAP
• Description: IC DAC QUAD SERIAL 8BIT 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX509BCAP

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 800mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
This command resets DOUT to transition at SCLK's falling
edge. Once this command is issued, the phase of DOUT is
latched and will not change except on power-up or if the
specific command is issued that sets the phase to rising
edge.
The same command also updates all DAC registers with
the contents of their respective input registers, identical to
the “LDAC” command.
LDAC is typically used in 4-wire interfaces (Figure 7).
LDAC allows asynchronous hardware control of the DAC
outputs and is level-sensitive. With LDAC low, the DAC reg-
isters are transparent and any time an input register is
updated, the DAC output immediately follows.
Strobing the CLR pin low causes an asynchronous clear of
input and DAC registers and sets all DAC outputs to zero.
Similar to the LDAC pin, CLR can be invoked at any time,
typically when the device is not selected (CS = H). When
the DAC data is all zeros, this function is equivalent to the
"Update all DACs from Shift Registers" command.
Digital inputs and outputs are compatible with both TTL and
5V CMOS logic. The power-supply current (I
on the input logic levels. Using CMOS logic to drive CS,
SCLK, DIN, CLR and LDAC turns off the internal level trans-
lators and minimizes supply currents.
DOUT is the output of the internal shift register. DOUT can be
programmed to clock out data on SCLK's falling edge (mode
0) or rising edge (mode 1). In mode 0, output data lags the
input data by 12.5 clock cycles, maintaining compatibility with
Microwire, SPI, and QSPI. In mode 1, output data lags the input
by 12 clock cycles. On power-up, DOUT defaults to mode 1
timing. DOUT never three-states; it always actively drives either
high or low and remains unchanged when CS is high.
The MAX509/MAX510 are Microwire, SPI, and QSPI compati-
ble. For SPI and QSPI, clear the CPOL and CPHA configura-
tion bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA
= 1 configuration can also be used if the DOUT output is
ignored.
(LDAC = x)
12
A1
1
______________________________________________________________________________________
A0
0
C1
1
Set DOUT Phase – SCLK Falling (Mode 0)
C0
0
D7
Interfacing to the Microprocessor
x
D6
x
LDAC Operation (Hardware)
Digital Inputs and Outputs
D5
x
Clear DACs with CLR
D4
x
Serial Data Output
D3
x
DD
D2
x
) depends
D1 D0
x
x
The MAX509/MAX510 can interface with Intel's
80C5X/80C3X family in mode 0 if the SCLK clock polarity is
inverted. More universally, if a serial port is not available,
three lines from one of the parallel ports can be used for bit
manipulation.
Digital feedthrough at the voltage outputs is greatly mini-
mized by operating the serial clock only to update the regis-
ters. Also see the Clock Feedthrough photo in the Typical
Operating Characteristics section. The clock idle state is low.
Any number of MAX509/MAX510s can be daisy-chained by
connecting the DOUT pin of one device to the DIN pin of the
following device in the chain. The NOP instruction (Table 1)
allows data to be passed from DIN to DOUT without chang-
ing the input or DAC registers of the passing device. A three-
wire interface updates daisy-chained or individual
MAX509/MAX510s simultaneously by bringing CS high.
Figure 4. Connections for MICROWIRE
Figure 5. Connections for SPI
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.
MAX509
MAX510
MAX509
MAX510
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
Daisy-Chaining Devices
CPOL = 0, CPHA = 0
SK
SO
SI
I/0
MISO
MOSI
SCK
I/0
MICROWIRE
PORT
PORT
SPI