LFXP2-17E-5F484I Lattice, LFXP2-17E-5F484I Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP2-17E-5F484I
Manufacturer Part Number
LFXP2-17E-5F484I
Description
FPGA LatticeXP2 Family 17000 Cells Flash Technology 1.2V 484-Pin FBGA
Manufacturer
Lattice
Datasheet
1.LFXP2-40E-5FN484I.pdf
(92 pages)
Specifications of LFXP2-17E-5F484I
Package
484FBGA
Family Name
LatticeXP2
Device Logic Units
17000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
358
Ram Bits
282624
Re-programmability Support
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-5F484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-5. Clock Divider Connections
Clock Distribution Network
LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based sec-
ondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to sup-
port high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock
inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs
and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There
are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources.
CLKOP (GPLL)
ECLK
RELEASE
RST
2-8
CLKDIV
LatticeXP2 Family Data Sheet
÷1
÷2
÷4
÷8
Architecture
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